Commit 6ae4a57a authored by Mark Cave-Ayland's avatar Mark Cave-Ayland Committed by David Gibson
Browse files

target/ppc: introduce GEN_VSX_HELPER_R2_AB macro to fpu_helper.c 



Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_R2_AB macro which performs the decode based
upon rA and rB at translation time.

Signed-off-by: default avatarMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-Id: <20190616123751.781-13-mark.cave-ayland@ilande.co.uk>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 99229620

target/ppc/fpu_helper.c

+4 −6
Original line number Diff line number Diff line
@@ -2452,10 +2452,9 @@ void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode, 
    do_float_check_status(env, GETPC());

}



void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode)

void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode,

                       ppc_vsr_t *xa, ppc_vsr_t *xb)

{

    ppc_vsr_t *xa = &env->vsr[rA(opcode) + 32];

    ppc_vsr_t *xb = &env->vsr[rB(opcode) + 32];

    int64_t exp_a, exp_b;

    uint32_t cc;
@@ -2531,10 +2530,9 @@ VSX_SCALAR_CMP(xscmpodp, 1) 
VSX_SCALAR_CMP(xscmpudp, 0)



#define VSX_SCALAR_CMPQ(op, ordered)                                    \

void helper_##op(CPUPPCState *env, uint32_t opcode)                     \

void helper_##op(CPUPPCState *env, uint32_t opcode,                     \

                 ppc_vsr_t *xa, ppc_vsr_t *xb)                          \

{                                                                       \

    ppc_vsr_t *xa = &env->vsr[rA(opcode) + 32];                         \

    ppc_vsr_t *xb = &env->vsr[rB(opcode) + 32];                         \

    uint32_t cc = 0;                                                    \

    bool vxsnan_flag = false, vxvc_flag = false;                        \

                                                                        \

target/ppc/helper.h

+3 −3
Original line number Diff line number Diff line
@@ -390,11 +390,11 @@ DEF_HELPER_4(xscmpgtdp, void, env, vsr, vsr, vsr) 
DEF_HELPER_4(xscmpgedp, void, env, vsr, vsr, vsr)

DEF_HELPER_4(xscmpnedp, void, env, vsr, vsr, vsr)

DEF_HELPER_4(xscmpexpdp, void, env, i32, vsr, vsr)

DEF_HELPER_2(xscmpexpqp, void, env, i32)

DEF_HELPER_4(xscmpexpqp, void, env, i32, vsr, vsr)

DEF_HELPER_4(xscmpodp, void, env, i32, vsr, vsr)

DEF_HELPER_4(xscmpudp, void, env, i32, vsr, vsr)

DEF_HELPER_2(xscmpoqp, void, env, i32)

DEF_HELPER_2(xscmpuqp, void, env, i32)

DEF_HELPER_4(xscmpoqp, void, env, i32, vsr, vsr)

DEF_HELPER_4(xscmpuqp, void, env, i32, vsr, vsr)

DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr)

DEF_HELPER_4(xsmindp, void, env, vsr, vsr, vsr)

DEF_HELPER_5(xsmaxcdp, void, env, i32, vsr, vsr, vsr)

target/ppc/translate/vsx-impl.inc.c

+21 −3
Original line number Diff line number Diff line
@@ -1133,6 +1133,24 @@ static void gen_##name(DisasContext *ctx) \ 
    tcg_temp_free_ptr(xb);                                                    \

}



#define GEN_VSX_HELPER_R2_AB(name, op1, op2, inval, type)                     \

static void gen_##name(DisasContext *ctx)                                     \

{                                                                             \

    TCGv_i32 opc;                                                             \

    TCGv_ptr xa, xb;                                                          \

    if (unlikely(!ctx->vsx_enabled)) {                                        \

        gen_exception(ctx, POWERPC_EXCP_VSXU);                                \

        return;                                                               \

    }                                                                         \

    opc = tcg_const_i32(ctx->opcode);                                         \

    xa = gen_vsr_ptr(rA(ctx->opcode) + 32);                                   \

    xb = gen_vsr_ptr(rB(ctx->opcode) + 32);                                   \

    gen_helper_##name(cpu_env, opc, xa, xb);                                  \

    tcg_temp_free_i32(opc);                                                   \

    tcg_temp_free_ptr(xa);                                                    \

    tcg_temp_free_ptr(xb);                                                    \

}



#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \

static void gen_##name(DisasContext *ctx)                     \

{                                                             \
@@ -1176,11 +1194,11 @@ GEN_VSX_HELPER_X3(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300) 
GEN_VSX_HELPER_X3(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300)

GEN_VSX_HELPER_X3(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300)

GEN_VSX_HELPER_X2_AB(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300)

GEN_VSX_HELPER_2(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300)

GEN_VSX_HELPER_R2_AB(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300)

GEN_VSX_HELPER_X2_AB(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)

GEN_VSX_HELPER_X2_AB(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)

GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)

GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)

GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)

GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)

GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)

GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX)

GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)