Commit 6a80e088 authored by Richard Henderson's avatar Richard Henderson Committed by Richard Henderson
Browse files

target-alpha: Disable interrupts properly. 



Interrupts are disabled in PALmode, and when the PS IL is high enough.

Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent a18ad893

cpu-exec.c

+30 −3
Original line number Diff line number Diff line
@@ -488,10 +488,37 @@ int cpu_exec(CPUState *env1) 
                        next_tb = 0;

                    }

#elif defined(TARGET_ALPHA)

                    {

                        int idx = -1;

                        /* ??? This hard-codes the OSF/1 interrupt levels.  */

		        switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {

                        case 0 ... 3:

                            if (interrupt_request & CPU_INTERRUPT_HARD) {

                                idx = EXCP_DEV_INTERRUPT;

                            }

                            /* FALLTHRU */

                        case 4:

                            if (interrupt_request & CPU_INTERRUPT_TIMER) {

                                idx = EXCP_CLK_INTERRUPT;

                            }

                            /* FALLTHRU */

                        case 5:

                            if (interrupt_request & CPU_INTERRUPT_SMP) {

                                idx = EXCP_SMP_INTERRUPT;

                            }

                            /* FALLTHRU */

                        case 6:

                            if (interrupt_request & CPU_INTERRUPT_MCHK) {

                                idx = EXCP_MCHK;

                            }

                        }

                        if (idx >= 0) {

                            env->exception_index = idx;

                            env->error_code = 0;

                            do_interrupt(env);

                            next_tb = 0;

                        }

                    }

#elif defined(TARGET_CRIS)

                    if (interrupt_request & CPU_INTERRUPT_HARD

                        && (env->pregs[PR_CCS] & I_FLAG)

target-alpha/cpu.h

+5 −0
Original line number Diff line number Diff line
@@ -315,6 +315,11 @@ enum { 
    EXCP_STQ_C,

};



/* Alpha-specific interrupt pending bits.  */

#define CPU_INTERRUPT_TIMER	CPU_INTERRUPT_TGT_EXT_0

#define CPU_INTERRUPT_SMP	CPU_INTERRUPT_TGT_EXT_1

#define CPU_INTERRUPT_MCHK	CPU_INTERRUPT_TGT_EXT_2



/* Hardware interrupt (entInt) constants.  */

enum {

    INT_K_IP,

target-alpha/exec.h

+11 −1
Original line number Diff line number Diff line
@@ -39,7 +39,17 @@ register struct CPUAlphaState *env asm(AREG0); 


static inline int cpu_has_work(CPUState *env)

{

    return (env->interrupt_request & CPU_INTERRUPT_HARD);

    /* Here we are checking to see if the CPU should wake up from HALT.

       We will have gotten into this state only for WTINT from PALmode.  */

    /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU

       asleep even if (some) interrupts have been asserted.  For now, 

       assume that if a CPU really wants to stay asleep, it will mask

       interrupts at the chipset level, which will prevent these bits

       from being set in the first place.  */

    return env->interrupt_request & (CPU_INTERRUPT_HARD

                                     | CPU_INTERRUPT_TIMER

                                     | CPU_INTERRUPT_SMP

                                     | CPU_INTERRUPT_MCHK);

}



static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)