Commit 6a4e1771 authored by Blue Swirl's avatar Blue Swirl
Browse files

Remove Sun4c, Sun4d and a few CPUs 



Sun4c and Sun4d architectures and related CPUs are not fully implemented
(especially Sun4c MMU) and there has been no interest for them.

Likewise, a few CPUs (Cypress, Ross etc) are only half implemented.

Remove the machines and CPUs, they can be re-added if needed later.

Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
parent 4f6ab397

hw/intc/Makefile.objs

+1 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ common-obj-$(CONFIG_ETRAXFS) += etraxfs_pic.o 
common-obj-$(CONFIG_IMX) += imx_avic.o

common-obj-$(CONFIG_LM32) += lm32_pic.o

common-obj-$(CONFIG_REALVIEW) += realview_gic.o

common-obj-$(CONFIG_SLAVIO) += sbi.o slavio_intctl.o sun4c_intctl.o

common-obj-$(CONFIG_SLAVIO) += slavio_intctl.o

common-obj-$(CONFIG_IOAPIC) += ioapic_common.o

common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o

hw/intc/sbi.c

deleted100644 → 0
+0 −156
Original line number Diff line number Diff line 
/*

 * QEMU Sparc SBI interrupt controller emulation

 *

 * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */



#include "hw/sysbus.h"



//#define DEBUG_IRQ



#ifdef DEBUG_IRQ

#define DPRINTF(fmt, ...)                                       \

    do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)

#else

#define DPRINTF(fmt, ...)

#endif



#define MAX_CPUS 16



#define SBI_NREGS 16



typedef struct SBIState {

    SysBusDevice busdev;

    MemoryRegion iomem;

    uint32_t regs[SBI_NREGS];

    uint32_t intreg_pending[MAX_CPUS];

    qemu_irq cpu_irqs[MAX_CPUS];

    uint32_t pil_out[MAX_CPUS];

} SBIState;



#define SBI_SIZE (SBI_NREGS * 4)



static void sbi_set_irq(void *opaque, int irq, int level)

{

}



static uint64_t sbi_mem_read(void *opaque, hwaddr addr,

                             unsigned size)

{

    SBIState *s = opaque;

    uint32_t saddr, ret;



    saddr = addr >> 2;

    switch (saddr) {

    default:

        ret = s->regs[saddr];

        break;

    }

    DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);



    return ret;

}



static void sbi_mem_write(void *opaque, hwaddr addr,

                          uint64_t val, unsigned dize)

{

    SBIState *s = opaque;

    uint32_t saddr;



    saddr = addr >> 2;

    DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, (int)val);

    switch (saddr) {

    default:

        s->regs[saddr] = val;

        break;

    }

}



static const MemoryRegionOps sbi_mem_ops = {

    .read = sbi_mem_read,

    .write = sbi_mem_write,

    .endianness = DEVICE_NATIVE_ENDIAN,

    .valid = {

        .min_access_size = 4,

        .max_access_size = 4,

    },

};



static const VMStateDescription vmstate_sbi = {

    .name ="sbi",

    .version_id = 1,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_UINT32_ARRAY(intreg_pending, SBIState, MAX_CPUS),

        VMSTATE_END_OF_LIST()

    }

};



static void sbi_reset(DeviceState *d)

{

    SBIState *s = container_of(d, SBIState, busdev.qdev);

    unsigned int i;



    for (i = 0; i < MAX_CPUS; i++) {

        s->intreg_pending[i] = 0;

    }

}



static int sbi_init1(SysBusDevice *dev)

{

    SBIState *s = FROM_SYSBUS(SBIState, dev);

    unsigned int i;



    qdev_init_gpio_in(&dev->qdev, sbi_set_irq, 32 + MAX_CPUS);

    for (i = 0; i < MAX_CPUS; i++) {

        sysbus_init_irq(dev, &s->cpu_irqs[i]);

    }



    memory_region_init_io(&s->iomem, &sbi_mem_ops, s, "sbi", SBI_SIZE);

    sysbus_init_mmio(dev, &s->iomem);



    return 0;

}



static void sbi_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);



    k->init = sbi_init1;

    dc->reset = sbi_reset;

    dc->vmsd = &vmstate_sbi;

}



static const TypeInfo sbi_info = {

    .name          = "sbi",

    .parent        = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(SBIState),

    .class_init    = sbi_class_init,

};



static void sbi_register_types(void)

{

    type_register_static(&sbi_info);

}



type_init(sbi_register_types)

hw/intc/sun4c_intctl.c

deleted100644 → 0
+0 −208
Original line number Diff line number Diff line 
/*

 * QEMU Sparc Sun4c interrupt controller emulation

 *

 * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */



#include "hw/hw.h"

#include "hw/sparc/sun4m.h"

#include "monitor/monitor.h"

#include "hw/sysbus.h"



//#define DEBUG_IRQ_COUNT

//#define DEBUG_IRQ



#ifdef DEBUG_IRQ

#define DPRINTF(fmt, ...)                                       \

    do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)

#else

#define DPRINTF(fmt, ...)

#endif



/*

 * Registers of interrupt controller in sun4c.

 *

 */



#define MAX_PILS 16



typedef struct Sun4c_INTCTLState {

    SysBusDevice busdev;

    MemoryRegion iomem;

#ifdef DEBUG_IRQ_COUNT

    uint64_t irq_count;

#endif

    qemu_irq cpu_irqs[MAX_PILS];

    const uint32_t *intbit_to_level;

    uint32_t pil_out;

    uint8_t reg;

    uint8_t pending;

} Sun4c_INTCTLState;



#define INTCTL_SIZE 1



static void sun4c_check_interrupts(void *opaque);



static uint64_t sun4c_intctl_mem_read(void *opaque, hwaddr addr,

                                      unsigned size)

{

    Sun4c_INTCTLState *s = opaque;

    uint32_t ret;



    ret = s->reg;

    DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);



    return ret;

}



static void sun4c_intctl_mem_write(void *opaque, hwaddr addr,

                                   uint64_t val, unsigned size)

{

    Sun4c_INTCTLState *s = opaque;



    DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, (unsigned)val);

    val &= 0xbf;

    s->reg = val;

    sun4c_check_interrupts(s);

}



static const MemoryRegionOps sun4c_intctl_mem_ops = {

    .read = sun4c_intctl_mem_read,

    .write = sun4c_intctl_mem_write,

    .endianness = DEVICE_NATIVE_ENDIAN,

    .valid = {

        .min_access_size = 1,

        .max_access_size = 1,

    },

};



static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };



static void sun4c_check_interrupts(void *opaque)

{

    Sun4c_INTCTLState *s = opaque;

    uint32_t pil_pending;

    unsigned int i;



    pil_pending = 0;

    if (s->pending && !(s->reg & 0x80000000)) {

        for (i = 0; i < 8; i++) {

            if (s->pending & (1 << i))

                pil_pending |= 1 << intbit_to_level[i];

        }

    }



    for (i = 0; i < MAX_PILS; i++) {

        if (pil_pending & (1 << i)) {

            if (!(s->pil_out & (1 << i)))

                qemu_irq_raise(s->cpu_irqs[i]);

        } else {

            if (s->pil_out & (1 << i))

                qemu_irq_lower(s->cpu_irqs[i]);

        }

    }

    s->pil_out = pil_pending;

}



/*

 * "irq" here is the bit number in the system interrupt register

 */

static void sun4c_set_irq(void *opaque, int irq, int level)

{

    Sun4c_INTCTLState *s = opaque;

    uint32_t mask = 1 << irq;

    uint32_t pil = intbit_to_level[irq];



    DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,

            level);

    if (pil > 0) {

        if (level) {

#ifdef DEBUG_IRQ_COUNT

            s->irq_count++;

#endif

            s->pending |= mask;

        } else {

            s->pending &= ~mask;

        }

        sun4c_check_interrupts(s);

    }

}



static const VMStateDescription vmstate_sun4c_intctl = {

    .name ="sun4c_intctl",

    .version_id = 1,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_UINT8(reg, Sun4c_INTCTLState),

        VMSTATE_UINT8(pending, Sun4c_INTCTLState),

        VMSTATE_END_OF_LIST()

    }

};



static void sun4c_intctl_reset(DeviceState *d)

{

    Sun4c_INTCTLState *s = container_of(d, Sun4c_INTCTLState, busdev.qdev);



    s->reg = 1;

    s->pending = 0;

}



static int sun4c_intctl_init1(SysBusDevice *dev)

{

    Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev);

    unsigned int i;



    memory_region_init_io(&s->iomem, &sun4c_intctl_mem_ops, s,

                          "intctl", INTCTL_SIZE);

    sysbus_init_mmio(dev, &s->iomem);

    qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);



    for (i = 0; i < MAX_PILS; i++) {

        sysbus_init_irq(dev, &s->cpu_irqs[i]);

    }



    return 0;

}



static void sun4c_intctl_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);



    k->init = sun4c_intctl_init1;

    dc->reset = sun4c_intctl_reset;

    dc->vmsd = &vmstate_sun4c_intctl;

}



static const TypeInfo sun4c_intctl_info = {

    .name          = "sun4c_intctl",

    .parent        = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(Sun4c_INTCTLState),

    .class_init    = sun4c_intctl_class_init,

};



static void sun4c_intctl_register_types(void)

{

    type_register_static(&sun4c_intctl_info);

}



type_init(sun4c_intctl_register_types)

hw/sparc/sun4m.c

+2 −461

File changed.

Preview size limit exceeded, changes collapsed.

qemu-doc.texi

+3 −7
Original line number Diff line number Diff line
@@ -1958,15 +1958,11 @@ SPARCbook 
The emulation is somewhat complete. SMP up to 16 CPUs is supported,

but Linux limits the number of usable CPUs to 4.



It's also possible to simulate a SPARCstation 2 (sun4c architecture),

SPARCserver 1000, or SPARCcenter 2000 (sun4d architecture), but these

emulators are not usable yet.



QEMU emulates the following sun4m/sun4c/sun4d peripherals:

QEMU emulates the following sun4m peripherals:



@itemize @minus

@item

IOMMU or IO-UNITs

IOMMU

@item

TCX Frame buffer

@item
@@ -2019,7 +2015,7 @@ qemu-system-sparc -prom-env 'auto-boot?=false' \ 
 -prom-env 'boot-device=sd(0,2,0):d' -prom-env 'boot-args=linux single'

@end example



@item -M [SS-4|SS-5|SS-10|SS-20|SS-600MP|LX|Voyager|SPARCClassic] [|SPARCbook|SS-2|SS-1000|SS-2000]

@item -M [SS-4|SS-5|SS-10|SS-20|SS-600MP|LX|Voyager|SPARCClassic] [|SPARCbook]



Set the emulated machine type. Default is SS-5.