Commit 69f87f71 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140804' into staging 



target-arm queue:
 * Set PC correctly when loading AArch64 ELF files
 * sdhci: Fix ADMA dma_memory_read access
 * some more foundational work for EL2/EL3 support
 * fix bugs which reveal themselves if the TARGET_PAGE_SIZE
   is not set to 1K

# gpg: Signature made Mon 04 Aug 2014 14:51:34 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20140804:
  target-arm: A64: fix TLB flush instructions
  target-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault
  target-arm: Fix bit test in sp_el0_access
  target-arm: Add FAR_EL2 and 3
  target-arm: Add ESR_EL2 and 3
  target-arm: Make far_el1 an array
  target-arm: A64: Respect SPSEL when taking exceptions
  target-arm: A64: Respect SPSEL in ERET SP restore
  target-arm: A64: Break out aarch64_save/restore_sp
  sd: sdhci: Fix ADMA dma_memory_read access
  hw/arm/virt: formatting: memory map
  hw/arm/boot: Set PC correctly when loading AArch64 ELF files

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents cc11a062 dbb1fb27

hw/arm/boot.c

+6 −2
Original line number Diff line number Diff line
@@ -417,8 +417,12 @@ static void do_cpu_reset(void *opaque) 
    if (info) {

        if (!info->is_linux) {

            /* Jump to the entry point.  */

            if (env->aarch64) {

                env->pc = info->entry;

            } else {

                env->regs[15] = info->entry & 0xfffffffe;

                env->thumb = info->entry & 1;

            }

        } else {

            if (CPU(cpu) == first_cpu) {

                if (env->aarch64) {

hw/arm/virt.c

+8 −8
Original line number Diff line number Diff line
@@ -98,14 +98,14 @@ typedef struct VirtBoardInfo { 
 */

static const MemMapEntry a15memmap[] = {

    /* Space up to 0x8000000 is reserved for a boot ROM */

    [VIRT_FLASH] = { 0, 0x8000000 },

    [VIRT_CPUPERIPHS] = { 0x8000000, 0x20000 },

    [VIRT_FLASH] =      {          0, 0x08000000 },

    [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },

    /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */

    [VIRT_GIC_DIST] = { 0x8000000, 0x10000 },

    [VIRT_GIC_CPU] = { 0x8010000, 0x10000 },

    [VIRT_UART] = { 0x9000000, 0x1000 },

    [VIRT_RTC] = { 0x9010000, 0x1000 },

    [VIRT_MMIO] = { 0xa000000, 0x200 },

    [VIRT_GIC_DIST] =   { 0x08000000, 0x00010000 },

    [VIRT_GIC_CPU] =    { 0x08010000, 0x00010000 },

    [VIRT_UART] =       { 0x09000000, 0x00001000 },

    [VIRT_RTC] =        { 0x09010000, 0x00001000 },

    [VIRT_MMIO] =       { 0x0a000000, 0x00000200 },

    /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */

    /* 0x10000000 .. 0x40000000 reserved for PCI */

    [VIRT_MEM] =        { 0x40000000, 30ULL * 1024 * 1024 * 1024 },

hw/sd/sdhci.c

+2 −1
Original line number Diff line number Diff line
@@ -702,7 +702,8 @@ static void sdhci_do_adma(SDHCIState *s) 
                        length -= block_size - begin;

                    }

                    dma_memory_read(&address_space_memory, dscr.addr,

                                    &s->fifo_buffer[begin], s->data_count);

                                    &s->fifo_buffer[begin],

                                    s->data_count - begin);

                    dscr.addr += s->data_count - begin;

                    if (s->data_count == block_size) {

                        for (n = 0; n < block_size; n++) {

target-arm/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -447,7 +447,7 @@ static void arm1026_initfn(Object *obj) 
        ARMCPRegInfo ifar = {

            .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,

            .access = PL1_RW,

            .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1),

            .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),

            .resetvalue = 0

        };

        define_one_arm_cp_reg(cpu, &ifar);

target-arm/cpu.h

+2 −2
Original line number Diff line number Diff line
@@ -185,9 +185,9 @@ typedef struct CPUARMState { 
        uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */

        uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */

        uint32_t ifsr_el2; /* Fault status registers.  */

        uint64_t esr_el[2];

        uint64_t esr_el[4];

        uint32_t c6_region[8]; /* MPU base/size registers.  */

        uint64_t far_el1; /* Fault address registers.  */

        uint64_t far_el[4]; /* Fault address registers.  */

        uint64_t par_el1;  /* Translation result. */

        uint32_t c9_insn; /* Cache lockdown registers.  */

        uint32_t c9_data;