Commit 69ceea64 authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset 



When the PMSAv7 implementation was originally added it was for R profile
CPUs only, and reset was handled using the cpreg .resetfn hooks.
Unfortunately for M profile cores this doesn't work, because they do
not register any cpregs. Move the reset handling into arm_cpu_reset(),
where it will work for both R profile and M profile cores.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1501153150-19984-5-git-send-email-peter.maydell@linaro.org
parent 8531eb4f

target/arm/cpu.c

+14 −0
Original line number Diff line number Diff line
@@ -232,6 +232,20 @@ static void arm_cpu_reset(CPUState *s) 


    env->vfp.xregs[ARM_VFP_FPEXC] = 0;

#endif



    if (arm_feature(env, ARM_FEATURE_PMSA) &&

        arm_feature(env, ARM_FEATURE_V7)) {

        if (cpu->pmsav7_dregion > 0) {

            memset(env->pmsav7.drbar, 0,

                   sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);

            memset(env->pmsav7.drsr, 0,

                   sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);

            memset(env->pmsav7.dracr, 0,

                   sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);

        }

        env->pmsav7.rnr = 0;

    }



    set_flush_to_zero(1, &env->vfp.standard_fp_status);

    set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);

    set_default_nan_mode(1, &env->vfp.standard_fp_status);

target/arm/helper.c

+12 −16
Original line number Diff line number Diff line
@@ -2404,18 +2404,6 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, 
    *u32p = value;

}



static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)

{

    ARMCPU *cpu = arm_env_get_cpu(env);

    uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);



    if (!u32p) {

        return;

    }



    memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);

}



static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,

                              uint64_t value)

{
@@ -2433,22 +2421,30 @@ static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, 
}



static const ARMCPRegInfo pmsav7_cp_reginfo[] = {

    /* Reset for all these registers is handled in arm_cpu_reset(),

     * because the PMSAv7 is also used by M-profile CPUs, which do

     * not register cpregs but still need the state to be reset.

     */

    { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,

      .access = PL1_RW, .type = ARM_CP_NO_RAW,

      .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),

      .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },

      .readfn = pmsav7_read, .writefn = pmsav7_write,

      .resetfn = arm_cp_reset_ignore },

    { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,

      .access = PL1_RW, .type = ARM_CP_NO_RAW,

      .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),

      .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },

      .readfn = pmsav7_read, .writefn = pmsav7_write,

      .resetfn = arm_cp_reset_ignore },

    { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,

      .access = PL1_RW, .type = ARM_CP_NO_RAW,

      .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),

      .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },

      .readfn = pmsav7_read, .writefn = pmsav7_write,

      .resetfn = arm_cp_reset_ignore },

    { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,

      .access = PL1_RW,

      .fieldoffset = offsetof(CPUARMState, pmsav7.rnr),

      .writefn = pmsav7_rgnr_write },

      .writefn = pmsav7_rgnr_write,

      .resetfn = arm_cp_reset_ignore },

    REGINFO_SENTINEL

};