Commit 68130236 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement FMOV (general) for fp16 



Adding the fp16 moves to/from general registers.

Cc: qemu-stable@nongnu.org
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Tested-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent bcc531f0

target/arm/translate-a64.c

+21 −0
Original line number Diff line number Diff line
@@ -5700,6 +5700,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) 
            tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));

            clear_vec_high(s, true, rd);

            break;

        case 3:

            /* 16 bit */

            tmp = tcg_temp_new_i64();

            tcg_gen_ext16u_i64(tmp, tcg_rn);

            write_fp_dreg(s, rd, tmp);

            tcg_temp_free_i64(tmp);

            break;

        default:

            g_assert_not_reached();

        }

    } else {

        TCGv_i64 tcg_rd = cpu_reg(s, rd);
@@ -5717,6 +5726,12 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) 
            /* 64 bits from top half */

            tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));

            break;

        case 3:

            /* 16 bit */

            tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));

            break;

        default:

            g_assert_not_reached();

        }

    }

}
@@ -5756,6 +5771,12 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) 
        case 0xa: /* 64 bit */

        case 0xd: /* 64 bit to top half of quad */

            break;

        case 0x6: /* 16-bit float, 32-bit int */

        case 0xe: /* 16-bit float, 64-bit int */

            if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

                break;

            }

            /* fallthru */

        default:

            /* all other sf/type/rmode combinations are invalid */

            unallocated_encoding(s);