Commit 673b2d42 authored by Joel Stanley's avatar Joel Stanley Committed by Peter Maydell
Browse files

arm: Add Nordic Semiconductor nRF51 SoC 

The nRF51 is a Cortex-M0 microcontroller with an on-board radio module,
plus other common ARM SoC peripherals.

 http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf



This defines a basic model of the CPU and memory, with no peripherals
implemented at this stage.

Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
Message-id: 20180831220920.27113-3-joel@jms.id.au
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
[PMM: wrapped a few long lines]
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent c0066d1a

default-configs/arm-softmmu.mak

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@@ -101,6 +101,7 @@ CONFIG_STM32F2XX_SYSCFG=y 
CONFIG_STM32F2XX_ADC=y

CONFIG_STM32F2XX_SPI=y

CONFIG_STM32F205_SOC=y

CONFIG_NRF51_SOC=y



CONFIG_CMSDK_APB_TIMER=y

CONFIG_CMSDK_APB_DUALTIMER=y

hw/arm/Makefile.objs

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@@ -37,3 +37,4 @@ obj-$(CONFIG_IOTKIT) += iotkit.o 
obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o

obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o

obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o mcimx6ul-evk.o

obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o

hw/arm/nrf51_soc.c

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/*

 * Nordic Semiconductor nRF51 SoC

 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf

 *

 * Copyright 2018 Joel Stanley <joel@jms.id.au>

 *

 * This code is licensed under the GPL version 2 or later.  See

 * the COPYING file in the top-level directory.

 */



#include "qemu/osdep.h"

#include "qapi/error.h"

#include "qemu-common.h"

#include "hw/arm/arm.h"

#include "hw/sysbus.h"

#include "hw/boards.h"

#include "hw/devices.h"

#include "hw/misc/unimp.h"

#include "exec/address-spaces.h"

#include "sysemu/sysemu.h"

#include "qemu/log.h"

#include "cpu.h"



#include "hw/arm/nrf51_soc.h"



#define IOMEM_BASE      0x40000000

#define IOMEM_SIZE      0x20000000



#define FICR_BASE       0x10000000

#define FICR_SIZE       0x000000fc



#define FLASH_BASE      0x00000000

#define SRAM_BASE       0x20000000



#define PRIVATE_BASE    0xF0000000

#define PRIVATE_SIZE    0x10000000



/*

 * The size and base is for the NRF51822 part. If other parts

 * are supported in the future, add a sub-class of NRF51SoC for

 * the specific variants

 */

#define NRF51822_FLASH_SIZE     (256 * 1024)

#define NRF51822_SRAM_SIZE      (16 * 1024)



static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)

{

    NRF51State *s = NRF51_SOC(dev_soc);

    Error *err = NULL;



    if (!s->board_memory) {

        error_setg(errp, "memory property was not set");

        return;

    }



    object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",

            &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }



    memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);



    memory_region_init_rom(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size,

            &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash);



    memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);



    create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);

    create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);

    create_unimplemented_device("nrf51_soc.private",

                                PRIVATE_BASE, PRIVATE_SIZE);

}



static void nrf51_soc_init(Object *obj)

{

    NRF51State *s = NRF51_SOC(obj);



    memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);



    sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu),

                          TYPE_ARMV7M);

    qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",

                         ARM_CPU_TYPE_NAME("cortex-m0"));

    qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);

}



static Property nrf51_soc_properties[] = {

    DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,

                     MemoryRegion *),

    DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),

    DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,

                       NRF51822_FLASH_SIZE),

    DEFINE_PROP_END_OF_LIST(),

};



static void nrf51_soc_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);



    dc->realize = nrf51_soc_realize;

    dc->props = nrf51_soc_properties;

}



static const TypeInfo nrf51_soc_info = {

    .name          = TYPE_NRF51_SOC,

    .parent        = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(NRF51State),

    .instance_init = nrf51_soc_init,

    .class_init    = nrf51_soc_class_init,

};



static void nrf51_soc_types(void)

{

    type_register_static(&nrf51_soc_info);

}

type_init(nrf51_soc_types)

include/hw/arm/nrf51_soc.h

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/*

 * Nordic Semiconductor nRF51  SoC

 *

 * Copyright 2018 Joel Stanley <joel@jms.id.au>

 *

 * This code is licensed under the GPL version 2 or later.  See

 * the COPYING file in the top-level directory.

 */



#ifndef NRF51_SOC_H

#define NRF51_SOC_H



#include "hw/sysbus.h"

#include "hw/arm/armv7m.h"



#define TYPE_NRF51_SOC "nrf51-soc"

#define NRF51_SOC(obj) \

    OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC)



typedef struct NRF51State {

    /*< private >*/

    SysBusDevice parent_obj;



    /*< public >*/

    ARMv7MState cpu;



    MemoryRegion iomem;

    MemoryRegion sram;

    MemoryRegion flash;



    uint32_t sram_size;

    uint32_t flash_size;



    MemoryRegion *board_memory;



    MemoryRegion container;



} NRF51State;



#endif