Commit 671b0f36 authored by Hervé Poussineau's avatar Hervé Poussineau Committed by Aurelien Jarno
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Correctly identify multiple cpus in SMP systems 



Signed-off-by: default avatarHervé Poussineau <hpoussin@reactos.org>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
parent cf7c00d5

target-mips/op_helper.c

+1 −2
Original line number Diff line number Diff line
@@ -1359,8 +1359,7 @@ void helper_mtc0_cause (target_ulong arg1) 
void helper_mtc0_ebase (target_ulong arg1)

{

    /* vectored interrupts not implemented */

    /* Multi-CPU not implemented */

    env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);

    env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);

}



void helper_mtc0_config0 (target_ulong arg1)

target-mips/translate.c

+1 −2
Original line number Diff line number Diff line
@@ -12679,8 +12679,7 @@ void cpu_reset (CPUMIPSState *env) 
    env->CP0_Random = env->tlb->nb_tlb - 1;

    env->tlb->tlb_in_use = env->tlb->nb_tlb;

    env->CP0_Wired = 0;

    /* SMP not implemented */

    env->CP0_EBase = 0x80000000;

    env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF);

    env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);

    /* vectored interrupts not implemented, timer on int 7,

       no performance counters. */