Unverified Commit 67185dad authored by Michael Clark's avatar Michael Clark
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RISC-V: Clear mtval/stval on exceptions without info 



mtval/stval must be set on all exceptions but zero is
a legal value if there is no exception specific info.
Placing the instruction bytes for illegal instruction
exceptions in mtval/stval is an optional feature and
is currently not supported by QEMU RISC-V.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: default avatarMichael Clark <mjc@sifive.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
parent 33e3bc8d

target/riscv/helper.c

+8 −0
Original line number Diff line number Diff line
@@ -466,6 +466,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) 
                    ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr);

            }

            env->sbadaddr = env->badaddr;

        } else {

            /* otherwise we must clear sbadaddr/stval

             * todo: support populating stval on illegal instructions */

            env->sbadaddr = 0;

        }



        target_ulong s = env->mstatus;
@@ -487,6 +491,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) 
                    ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr);

            }

            env->mbadaddr = env->badaddr;

        } else {

            /* otherwise we must clear mbadaddr/mtval

             * todo: support populating mtval on illegal instructions */

            env->mbadaddr = 0;

        }



        target_ulong s = env->mstatus;