Commit 66991d11 authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by Leon Alrae
Browse files

target-mips: Fix DisasContext's ulri member initialization 



Set DisasContext's ulri member to 0 or 1 as with other bool members.

Signed-off-by: default avatarMaciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
Signed-off-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
parent 1a4d5700

target-mips/translate.c

+1 −1
Original line number Diff line number Diff line
@@ -19116,7 +19116,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, 
    ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1;

    /* Restore delay slot state from the tb context.  */

    ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */

    ctx.ulri = env->CP0_Config3 & (1 << CP0C3_ULRI);

    ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;

    restore_cpu_state(env, &ctx);

#ifdef CONFIG_USER_ONLY

        ctx.mem_idx = MIPS_HFLAG_UM;