Commit 664b7e3b authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word 



Separate shift + extract low will result in one extra insn
for hosts like RISC-V, MIPS, and Sparc.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190808202616.13782-8-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 5f8cd06e

target/arm/translate.c

+6 −12
Original line number Diff line number Diff line
@@ -1746,8 +1746,7 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) 
            if (insn & ARM_CP_RW_BIT) {                         /* TMRRC */

                iwmmxt_load_reg(cpu_V0, wrd);

                tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0);

                tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);

                tcg_gen_extrl_i64_i32(cpu_R[rdhi], cpu_V0);

                tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0);

            } else {                                    /* TMCRR */

                tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);

                iwmmxt_store_reg(cpu_V0, wrd);
@@ -2792,8 +2791,7 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn) 
        if (insn & ARM_CP_RW_BIT) {                     /* MRA */

            iwmmxt_load_reg(cpu_V0, acc);

            tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0);

            tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);

            tcg_gen_extrl_i64_i32(cpu_R[rdhi], cpu_V0);

            tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0);

            tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);

        } else {                                        /* MAR */

            tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
@@ -5990,8 +5988,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) 
                                gen_helper_neon_narrow_high_u16(tmp, cpu_V0);

                                break;

                            case 2:

                                tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);

                                tcg_gen_extrl_i64_i32(tmp, cpu_V0);

                                tcg_gen_extrh_i64_i32(tmp, cpu_V0);

                                break;

                            default: abort();

                            }
@@ -6005,8 +6002,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) 
                                break;

                            case 2:

                                tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);

                                tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);

                                tcg_gen_extrl_i64_i32(tmp, cpu_V0);

                                tcg_gen_extrh_i64_i32(tmp, cpu_V0);

                                break;

                            default: abort();

                            }
@@ -7239,9 +7235,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) 
                tmp = tcg_temp_new_i32();

                tcg_gen_extrl_i64_i32(tmp, tmp64);

                store_reg(s, rt, tmp);

                tcg_gen_shri_i64(tmp64, tmp64, 32);

                tmp = tcg_temp_new_i32();

                tcg_gen_extrl_i64_i32(tmp, tmp64);

                tcg_gen_extrh_i64_i32(tmp, tmp64);

                tcg_temp_free_i64(tmp64);

                store_reg(s, rt2, tmp);

            } else {
@@ -7350,8 +7345,7 @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val) 
    tcg_gen_extrl_i64_i32(tmp, val);

    store_reg(s, rlow, tmp);

    tmp = tcg_temp_new_i32();

    tcg_gen_shri_i64(val, val, 32);

    tcg_gen_extrl_i64_i32(tmp, val);

    tcg_gen_extrh_i64_i32(tmp, val);

    store_reg(s, rhigh, tmp);

}