Commit 65e4655c authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Move cpu_mmu_index out of line 



This function is, or will shortly become, too big to inline.

Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190108223129.5570-16-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent bd889f48

target/arm/cpu.h

+5 −43
Original line number Diff line number Diff line
@@ -2741,54 +2741,16 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 
}



/* Return the MMU index for a v7M CPU in the specified security and

 * privilege state

 * privilege state.

 */

static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,

                                                              bool secstate,

                                                              bool priv)

{

    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;



    if (priv) {

        mmu_idx |= ARM_MMU_IDX_M_PRIV;

    }



    if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {

        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;

    }



    if (secstate) {

        mmu_idx |= ARM_MMU_IDX_M_S;

    }



    return mmu_idx;

}

ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,

                                                bool secstate, bool priv);



/* Return the MMU index for a v7M CPU in the specified security state */

static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,

                                                     bool secstate)

{

    bool priv = arm_current_el(env) != 0;



    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);

}

ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);



/* Determine the current mmu_idx to use for normal loads/stores */

static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)

{

    int el = arm_current_el(env);



    if (arm_feature(env, ARM_FEATURE_M)) {

        ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);



        return arm_to_core_mmu_idx(mmu_idx);

    }



    if (el < 2 && arm_is_secure_below_el3(env)) {

        return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);

    }

    return el;

}

int cpu_mmu_index(CPUARMState *env, bool ifetch);



/* Indexes used when registering address spaces with cpu_address_space_init */

typedef enum ARMASIdx {

target/arm/helper.c

+44 −0
Original line number Diff line number Diff line
@@ -12949,6 +12949,50 @@ int fp_exception_el(CPUARMState *env, int cur_el) 
    return 0;

}



ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,

                                                bool secstate, bool priv)

{

    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;



    if (priv) {

        mmu_idx |= ARM_MMU_IDX_M_PRIV;

    }



    if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {

        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;

    }



    if (secstate) {

        mmu_idx |= ARM_MMU_IDX_M_S;

    }



    return mmu_idx;

}



/* Return the MMU index for a v7M CPU in the specified security state */

ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)

{

    bool priv = arm_current_el(env) != 0;



    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);

}



int cpu_mmu_index(CPUARMState *env, bool ifetch)

{

    int el = arm_current_el(env);



    if (arm_feature(env, ARM_FEATURE_M)) {

        ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);



        return arm_to_core_mmu_idx(mmu_idx);

    }



    if (el < 2 && arm_is_secure_below_el3(env)) {

        return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);

    }

    return el;

}



void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

                          target_ulong *cs_base, uint32_t *pflags)

{