Commit 650a379d authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190613-1' into staging 



target-arm queue:
 * convert aarch32 VFP decoder to decodetree
   (includes tightening up decode in a few places)
 * fix minor bugs in VFP short-vector handling
 * hw/core/bus.c: Only the main system bus can have no parent
 * smmuv3: Fix decoding of ID register range
 * Implement NSACR gating of floating point
 * Use tcg_gen_gvec_bitsel

# gpg: Signature made Thu 13 Jun 2019 15:15:39 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190613-1: (47 commits)
  target/arm: Fix short-vector increment behaviour
  target/arm: Convert float-to-integer VCVT insns to decodetree
  target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree
  target/arm: Convert VJCVT to decodetree
  target/arm: Convert integer-to-float insns to decodetree
  target/arm: Convert double-single precision conversion insns to decodetree
  target/arm: Convert VFP round insns to decodetree
  target/arm: Convert the VCVT-to-f16 insns to decodetree
  target/arm: Convert the VCVT-from-f16 insns to decodetree
  target/arm: Convert VFP comparison insns to decodetree
  target/arm: Convert VMOV (register) to decodetree
  target/arm: Convert VSQRT to decodetree
  target/arm: Convert VNEG to decodetree
  target/arm: Convert VABS to decodetree
  target/arm: Convert VMOV (imm) to decodetree
  target/arm: Convert VFP fused multiply-add insns to decodetree
  target/arm: Convert VDIV to decodetree
  target/arm: Convert VSUB to decodetree
  target/arm: Convert VADD to decodetree
  target/arm: Convert VNMUL to decodetree
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 785a602e 18cf951a

hw/arm/smmuv3.c

+1 −1
Original line number Diff line number Diff line
@@ -1232,7 +1232,7 @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset, 
                              uint64_t *data, MemTxAttrs attrs)

{

    switch (offset) {

    case A_IDREGS ... A_IDREGS + 0x1f:

    case A_IDREGS ... A_IDREGS + 0x2f:

        *data = smmuv3_idreg(offset - A_IDREGS);

        return MEMTX_OK;

    case A_IDR0 ... A_IDR5:

hw/core/bus.c

+9 −12
Original line number Diff line number Diff line
@@ -97,10 +97,9 @@ static void qbus_realize(BusState *bus, DeviceState *parent, const char *name) 
        bus->parent->num_child_bus++;

        object_property_add_child(OBJECT(bus->parent), bus->name, OBJECT(bus), NULL);

        object_unref(OBJECT(bus));

    } else if (bus != sysbus_get_default()) {

        /* TODO: once all bus devices are qdevified,

           only reset handler for main_system_bus should be registered here. */

        qemu_register_reset(qbus_reset_all_fn, bus);

    } else {

        /* The only bus without a parent is the main system bus */

        assert(bus == sysbus_get_default());

    }

}
@@ -109,18 +108,16 @@ static void bus_unparent(Object *obj) 
    BusState *bus = BUS(obj);

    BusChild *kid;



    /* Only the main system bus has no parent, and that bus is never freed */

    assert(bus->parent);



    while ((kid = QTAILQ_FIRST(&bus->children)) != NULL) {

        DeviceState *dev = kid->child;

        object_unparent(OBJECT(dev));

    }

    if (bus->parent) {

    QLIST_REMOVE(bus, sibling);

    bus->parent->num_child_bus--;

    bus->parent = NULL;

    } else {

        assert(bus != sysbus_get_default()); /* main_system_bus is never freed */

        qemu_unregister_reset(qbus_reset_all_fn, bus);

    }

}



void qbus_create_inplace(void *bus, size_t size, const char *typename,

scripts/decodetree.py

+1 −1
Original line number Diff line number Diff line
@@ -184,7 +184,7 @@ class Field: 
        return '{0}(insn, {1}, {2})'.format(extr, self.pos, self.len)



    def __eq__(self, other):

        return self.sign == other.sign and self.sign == other.sign

        return self.sign == other.sign and self.mask == other.mask



    def __ne__(self, other):

        return not self.__eq__(other)

target/arm/Makefile.objs

+13 −0
Original line number Diff line number Diff line
@@ -19,5 +19,18 @@ target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE) 
	  $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\

	  "GEN", $(TARGET_DIR)$@)



target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)

	$(call quiet-command,\

	  $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\

	  "GEN", $(TARGET_DIR)$@)



target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE)

	$(call quiet-command,\

	  $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\

	  "GEN", $(TARGET_DIR)$@)



target/arm/translate-sve.o: target/arm/decode-sve.inc.c

target/arm/translate.o: target/arm/decode-vfp.inc.c

target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c



obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o

target/arm/cpu.c

+6 −0
Original line number Diff line number Diff line
@@ -1609,6 +1609,8 @@ static void cortex_r5f_initfn(Object *obj) 


    cortex_r5_initfn(obj);

    set_feature(&cpu->env, ARM_FEATURE_VFP3);

    cpu->isar.mvfr0 = 0x10110221;

    cpu->isar.mvfr1 = 0x00000011;

}



static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
@@ -2021,6 +2023,10 @@ static void arm_max_initfn(Object *obj) 
        kvm_arm_set_cpu_features_from_host(cpu);

    } else {

        cortex_a15_initfn(obj);



        /* old-style VFP short-vector support */

        cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);



#ifdef CONFIG_USER_ONLY

        /* We don't set these in system emulation mode for the moment,

         * since we don't correctly set (all of) the ID registers to