Commit 64e0e2de authored by Edgar E. Iglesias's avatar Edgar E. Iglesias Committed by Peter Maydell
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target-arm: Add SCR_EL3 



Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1411718914-6608-3-git-send-email-edgar.iglesias@gmail.com
[PMM: apply offsetoflow32() to correct regdef]
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent f149e3e8

target-arm/cpu.h

+18 −1
Original line number Diff line number Diff line
@@ -172,7 +172,6 @@ typedef struct CPUARMState { 
        uint64_t c1_sys; /* System control register.  */

        uint64_t c1_coproc; /* Coprocessor access register.  */

        uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */

        uint32_t c1_scr; /* secure config register.  */

        uint64_t ttbr0_el1; /* MMU translation table base 0. */

        uint64_t ttbr1_el1; /* MMU translation table base 1. */

        uint64_t c2_control; /* MMU translation table base control.  */
@@ -185,6 +184,7 @@ typedef struct CPUARMState { 
        uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */

        uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */

        uint64_t hcr_el2; /* Hypervisor configuration register */

        uint64_t scr_el3; /* Secure configuration register.  */

        uint32_t ifsr_el2; /* Fault status registers.  */

        uint64_t esr_el[4];

        uint32_t c6_region[8]; /* MPU base/size registers.  */
@@ -602,6 +602,23 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 
#define HCR_ID        (1ULL << 33)

#define HCR_MASK      ((1ULL << 34) - 1)



#define SCR_NS                (1U << 0)

#define SCR_IRQ               (1U << 1)

#define SCR_FIQ               (1U << 2)

#define SCR_EA                (1U << 3)

#define SCR_FW                (1U << 4)

#define SCR_AW                (1U << 5)

#define SCR_NET               (1U << 6)

#define SCR_SMD               (1U << 7)

#define SCR_HCE               (1U << 8)

#define SCR_SIF               (1U << 9)

#define SCR_RW                (1U << 10)

#define SCR_ST                (1U << 11)

#define SCR_TWI               (1U << 12)

#define SCR_TWE               (1U << 13)

#define SCR_AARCH32_MASK      (0x3fff & ~(SCR_RW | SCR_ST))

#define SCR_AARCH64_MASK      (0x3fff & ~SCR_NET)



/* Return the current FPSCR value.  */

uint32_t vfp_get_fpscr(CPUARMState *env);

void vfp_set_fpscr(CPUARMState *env, uint32_t val);

target-arm/helper.c

+33 −2
Original line number Diff line number Diff line
@@ -747,6 +747,32 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, 
    raw_write(env, ri, value & ~0x1FULL);

}



static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

{

    /* We only mask off bits that are RES0 both for AArch64 and AArch32.

     * For bits that vary between AArch32/64, code needs to check the

     * current execution mode before directly using the feature bit.

     */

    uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;



    if (!arm_feature(env, ARM_FEATURE_EL2)) {

        valid_mask &= ~SCR_HCE;



        /* On ARMv7, SMD (or SCD as it is called in v7) is only

         * supported if EL2 exists. The bit is UNK/SBZP when

         * EL2 is unavailable. In QEMU ARMv7, we force it to always zero

         * when EL2 is unavailable.

         */

        if (arm_feature(env, ARM_FEATURE_V7)) {

            valid_mask &= ~SCR_SMD;

        }

    }



    /* Clear all-context RES0 bits.  */

    value &= valid_mask;

    raw_write(env, ri, value);

}



static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)

{

    ARMCPU *cpu = arm_env_get_cpu(env);
@@ -873,8 +899,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { 
      .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),

      .resetvalue = 0 },

    { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,

      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),

      .resetvalue = 0, },

      .access = PL1_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),

      .resetvalue = 0, .writefn = scr_write },

    { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,

      .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,

      .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
@@ -2309,6 +2335,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { 
      .access = PL3_RW, .writefn = vbar_write,

      .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),

      .resetvalue = 0 },

    { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,

      .type = ARM_CP_NO_MIGRATE,

      .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,

      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),

      .writefn = scr_write },

    REGINFO_SENTINEL

};