Commit 64bde0f3 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

hw/a*: pass owner to memory_region_init* functions 



Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent db10ca90

hw/acpi/core.c

+6 −3
Original line number Diff line number Diff line
@@ -419,7 +419,8 @@ void acpi_pm1_evt_init(ACPIREGS *ar, acpi_update_sci_fn update_sci, 
                       MemoryRegion *parent)

{

    ar->pm1.evt.update_sci = update_sci;

    memory_region_init_io(&ar->pm1.evt.io, NULL, &acpi_pm_evt_ops, ar, "acpi-evt", 4);

    memory_region_init_io(&ar->pm1.evt.io, memory_region_owner(parent),

                          &acpi_pm_evt_ops, ar, "acpi-evt", 4);

    memory_region_add_subregion(parent, 0, &ar->pm1.evt.io);

}
@@ -481,7 +482,8 @@ void acpi_pm_tmr_init(ACPIREGS *ar, acpi_update_sci_fn update_sci, 
{

    ar->tmr.update_sci = update_sci;

    ar->tmr.timer = qemu_new_timer_ns(vm_clock, acpi_pm_tmr_timer, ar);

    memory_region_init_io(&ar->tmr.io, NULL, &acpi_pm_tmr_ops, ar, "acpi-tmr", 4);

    memory_region_init_io(&ar->tmr.io, memory_region_owner(parent),

                          &acpi_pm_tmr_ops, ar, "acpi-tmr", 4);

    memory_region_add_subregion(parent, 8, &ar->tmr.io);

}
@@ -552,7 +554,8 @@ void acpi_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *parent, uint8_t s4_val) 
    ar->pm1.cnt.s4_val = s4_val;

    ar->wakeup.notify = acpi_notify_wakeup;

    qemu_register_wakeup_notifier(&ar->wakeup);

    memory_region_init_io(&ar->pm1.cnt.io, NULL, &acpi_pm_cnt_ops, ar, "acpi-cnt", 2);

    memory_region_init_io(&ar->pm1.cnt.io, memory_region_owner(parent),

                          &acpi_pm_cnt_ops, ar, "acpi-cnt", 2);

    memory_region_add_subregion(parent, 4, &ar->pm1.cnt.io);

}

hw/acpi/ich9.c

+5 −5
Original line number Diff line number Diff line
@@ -205,7 +205,7 @@ static void pm_powerdown_req(Notifier *n, void *opaque) 
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,

                  qemu_irq sci_irq)

{

    memory_region_init(&pm->io, NULL, "ich9-pm", ICH9_PMIO_SIZE);

    memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);

    memory_region_set_enabled(&pm->io, false);

    memory_region_add_subregion(pci_address_space_io(lpc_pci),

                                0, &pm->io);
@@ -215,12 +215,12 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, 
    acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, 2);



    acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);

    memory_region_init_io(&pm->io_gpe, NULL, &ich9_gpe_ops, pm, "apci-gpe0",

                          ICH9_PMIO_GPE0_LEN);

    memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,

                          "apci-gpe0", ICH9_PMIO_GPE0_LEN);

    memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);



    memory_region_init_io(&pm->io_smi, NULL, &ich9_smi_ops, pm, "apci-smi",

                          8);

    memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm,

                          "apci-smi", 8);

    memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);



    pm->irq = sci_irq;

hw/acpi/piix4.c

+7 −7
Original line number Diff line number Diff line
@@ -424,7 +424,7 @@ static int piix4_pm_initfn(PCIDevice *dev) 
    memory_region_add_subregion(pci_address_space_io(dev),

                                s->smb_io_base, &s->smb.io);



    memory_region_init(&s->io, NULL, "piix4-pm", 64);

    memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);

    memory_region_set_enabled(&s->io, false);

    memory_region_add_subregion(pci_address_space_io(dev),

                                0, &s->io);
@@ -671,19 +671,19 @@ static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, 
static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,

                                           PCIBus *bus, PIIX4PMState *s)

{

    memory_region_init_io(&s->io_gpe, NULL, &piix4_gpe_ops, s, "apci-gpe0",

                          GPE_LEN);

    memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,

                          "acpi-gpe0", GPE_LEN);

    memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);



    memory_region_init_io(&s->io_pci, NULL, &piix4_pci_ops, s, "apci-pci-hotplug",

                          PCI_HOTPLUG_SIZE);

    memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s,

                          "acpi-pci-hotplug", PCI_HOTPLUG_SIZE);

    memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR,

                                &s->io_pci);

    pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);



    qemu_for_each_cpu(piix4_init_cpu_status, &s->gpe_cpu);

    memory_region_init_io(&s->io_cpu, NULL, &cpu_hotplug_ops, s, "apci-cpu-hotplug",

                          PIIX4_PROC_LEN);

    memory_region_init_io(&s->io_cpu, OBJECT(s), &cpu_hotplug_ops, s,

                          "acpi-cpu-hotplug", PIIX4_PROC_LEN);

    memory_region_add_subregion(parent, PIIX4_PROC_BASE, &s->io_cpu);

    s->cpu_added_notifier.notify = piix4_cpu_added_req;

    qemu_register_cpu_added_notifier(&s->cpu_added_notifier);

hw/alpha/typhoon.c

+12 −9
Original line number Diff line number Diff line
@@ -741,7 +741,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, 


    /* Main memory region, 0x00.0000.0000.  Real hardware supports 32GB,

       but the address space hole reserved at this point is 8TB.  */

    memory_region_init_ram(&s->ram_region, NULL, "ram", ram_size);

    memory_region_init_ram(&s->ram_region, OBJECT(s), "ram", ram_size);

    vmstate_register_ram_global(&s->ram_region);

    memory_region_add_subregion(addr_space, 0, &s->ram_region);
@@ -750,22 +750,25 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, 
       the flash ROM.  I'm not sure that we need to implement it at all.  */



    /* Pchip0 CSRs, 0x801.8000.0000, 256MB.  */

    memory_region_init_io(&s->pchip.region, NULL, &pchip_ops, s, "pchip0", 256*MB);

    memory_region_init_io(&s->pchip.region, OBJECT(s), &pchip_ops, s, "pchip0",

                          256*MB);

    memory_region_add_subregion(addr_space, 0x80180000000ULL,

                                &s->pchip.region);



    /* Cchip CSRs, 0x801.A000.0000, 256MB.  */

    memory_region_init_io(&s->cchip.region, NULL, &cchip_ops, s, "cchip0", 256*MB);

    memory_region_init_io(&s->cchip.region, OBJECT(s), &cchip_ops, s, "cchip0",

                          256*MB);

    memory_region_add_subregion(addr_space, 0x801a0000000ULL,

                                &s->cchip.region);



    /* Dchip CSRs, 0x801.B000.0000, 256MB.  */

    memory_region_init_io(&s->dchip_region, NULL, &dchip_ops, s, "dchip0", 256*MB);

    memory_region_init_io(&s->dchip_region, OBJECT(s), &dchip_ops, s, "dchip0",

                          256*MB);

    memory_region_add_subregion(addr_space, 0x801b0000000ULL,

                                &s->dchip_region);



    /* Pchip0 PCI memory, 0x800.0000.0000, 4GB.  */

    memory_region_init(&s->pchip.reg_mem, NULL, "pci0-mem", 4*GB);

    memory_region_init(&s->pchip.reg_mem, OBJECT(s), "pci0-mem", 4*GB);

    memory_region_add_subregion(addr_space, 0x80000000000ULL,

                                &s->pchip.reg_mem);
@@ -773,8 +776,8 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, 
    /* ??? Ideally we drop the "system" i/o space on the floor and give the

       PCI subsystem the full address space reserved by the chipset.

       We can't do that until the MEM and IO paths in memory.c are unified.  */

    memory_region_init_io(&s->pchip.reg_io, NULL, &alpha_pci_bw_io_ops, NULL,

                          "pci0-io", 32*MB);

    memory_region_init_io(&s->pchip.reg_io, OBJECT(s), &alpha_pci_bw_io_ops,

                          NULL, "pci0-io", 32*MB);

    memory_region_add_subregion(addr_space, 0x801fc000000ULL,

                                &s->pchip.reg_io);
@@ -784,13 +787,13 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, 
    phb->bus = b;



    /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB.  */

    memory_region_init_io(&s->pchip.reg_iack, NULL, &alpha_pci_iack_ops, b,

    memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops, b,

                          "pci0-iack", 64*MB);

    memory_region_add_subregion(addr_space, 0x801f8000000ULL,

                                &s->pchip.reg_iack);



    /* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB.  */

    memory_region_init_io(&s->pchip.reg_conf, NULL, &alpha_pci_conf1_ops, b,

    memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &alpha_pci_conf1_ops, b,

                          "pci0-conf", 16*MB);

    memory_region_add_subregion(addr_space, 0x801fe000000ULL,

                                &s->pchip.reg_conf);

hw/arm/armv7m.c

+2 −2
Original line number Diff line number Diff line
@@ -124,8 +124,8 @@ static int bitband_init(SysBusDevice *dev) 
{

    BitBandState *s = FROM_SYSBUS(BitBandState, dev);



    memory_region_init_io(&s->iomem, NULL, &bitband_ops, &s->base, "bitband",

                          0x02000000);

    memory_region_init_io(&s->iomem, OBJECT(s), &bitband_ops, &s->base,

                          "bitband", 0x02000000);

    sysbus_init_mmio(dev, &s->iomem);

    return 0;

}