Commit 6311b19b authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170210' into staging 



target-arm queue:
 * aspeed: minor fixes
 * virt: declare fwcfg and virtio-mmio as DMA coherent in DT & ACPI
 * arm: enable basic TCG emulation of PMU for AArch64

# gpg: Signature made Fri 10 Feb 2017 18:06:30 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170210:
  aspeed/smc: use a modulo to check segment limits
  aspeed/smc: handle dummies only in fast read mode
  aspeed: remove useless comment on controller segment size
  aspeed: check for negative values returned by blk_getlength()
  hw/arm/virt: Declare fwcfg as dma cache coherent in dt
  hw/arm/virt: Declare fwcfg as dma cache coherent in ACPI
  hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI
  target-arm: Declare virtio-mmio as dma-coherent in dt
  target-arm: Enable vPMU support under TCG mode
  target-arm: Add support for PMU register PMINTENSET_EL1
  target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0
  target-arm: Add support for PMU register PMSELR_EL0

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 98b2faea b4cc583f

hw/arm/aspeed.c

+15 −7
Original line number Diff line number Diff line
@@ -113,9 +113,19 @@ static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 
{

    BlockBackend *blk = blk_by_legacy_dinfo(dinfo);

    uint8_t *storage;

    int64_t size;



    if (rom_size > blk_getlength(blk)) {

        rom_size = blk_getlength(blk);

    /* The block backend size should have already been 'validated' by

     * the creation of the m25p80 object.

     */

    size = blk_getlength(blk);

    if (size <= 0) {

        error_setg(errp, "failed to get flash size");

        return;

    }



    if (rom_size > size) {

        rom_size = size;

    }



    storage = g_new0(uint8_t, rom_size);
@@ -138,10 +148,6 @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 
        DriveInfo *dinfo = drive_get_next(IF_MTD);

        qemu_irq cs_line;



        /*

         * FIXME: check that we are not using a flash module exceeding

         * the controller segment size

         */

        fl->flash = ssi_create_slave_no_init(s->spi, flashtype);

        if (dinfo) {

            qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
@@ -200,7 +206,9 @@ static void aspeed_board_init(MachineState *machine, 


        /*

         * create a ROM region using the default mapping window size of

         * the flash module.

         * the flash module. The window size is 64MB for the AST2400

         * SoC and 128MB for the AST2500 SoC, which is twice as big as

         * needed by the flash modules of the Aspeed machines.

         */

        memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",

                               fl->size, &error_abort);

hw/arm/vexpress.c

+1 −0
Original line number Diff line number Diff line
@@ -452,6 +452,7 @@ static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 
                                       acells, addr, scells, size);

    qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);

    qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);

    qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);

    g_free(nodename);

    if (rc) {

        return -1;

hw/arm/virt-acpi-build.c

+2 −0
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) 
    aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));

    /* device present, functioning, decoding, not shown in UI */

    aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));

    aml_append(dev, aml_name_decl("_CCA", aml_int(1)));



    Aml *crs = aml_resource_template();

    aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
@@ -135,6 +136,7 @@ static void acpi_dsdt_add_virtio(Aml *scope, 
        Aml *dev = aml_device("VR%02u", i);

        aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));

        aml_append(dev, aml_name_decl("_UID", aml_int(i)));

        aml_append(dev, aml_name_decl("_CCA", aml_int(1)));



        Aml *crs = aml_resource_template();

        aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));

hw/arm/virt.c

+3 −1
Original line number Diff line number Diff line
@@ -471,7 +471,7 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) 
    CPU_FOREACH(cpu) {

        armcpu = ARM_CPU(cpu);

        if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU) ||

            !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) {

            (kvm_enabled() && !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ)))) {

            return;

        }

    }
@@ -797,6 +797,7 @@ static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 
        qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",

                               GIC_FDT_IRQ_TYPE_SPI, irq,

                               GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);

        qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);

        g_free(nodename);

    }

}
@@ -928,6 +929,7 @@ static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 
                            "compatible", "qemu,fw-cfg-mmio");

    qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",

                                 2, base, 2, size);

    qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);

    g_free(nodename);

    return fw_cfg;

}

hw/ssi/aspeed_smc.c

+8 −5
Original line number Diff line number Diff line
@@ -475,15 +475,15 @@ static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl, 
    AspeedSegments seg;



    aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + fl->id], &seg);

    if ((addr & (seg.size - 1)) != addr) {

    if ((addr % seg.size) != addr) {

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: invalid address 0x%08x for CS%d segment : "

                      "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",

                      s->ctrl->name, addr, fl->id, seg.addr,

                      seg.addr + seg.size);

        addr %= seg.size;

    }



    addr &= seg.size - 1;

    return addr;

}
@@ -536,11 +536,14 @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size) 
        /*

         * Use fake transfers to model dummy bytes. The value should

         * be configured to some non-zero value in fast read mode and

         * zero in read mode.

         * zero in read mode. But, as the HW allows inconsistent

         * settings, let's check for fast read mode.

         */

        if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {

            for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {

                ssi_transfer(fl->controller->spi, 0xFF);

            }

        }



        for (i = 0; i < size; i++) {

            ret |= ssi_transfer(s->spi, 0x0) << (8 * i);