Commit 63010795 authored by Yongbok Kim's avatar Yongbok Kim Committed by Aleksandar Markovic
Browse files

target/mips: Add reset state for PWSize and PWField registers 



Add reset state for PWSize and PWField registers. The reset state
is different for pre-R6 and R6 (and post-R6) ISAa.

Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarYongbok Kim <yongbok.kim@mips.com>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
parent 103be64c

target/mips/translate.c

+18 −0
Original line number Diff line number Diff line
@@ -26444,6 +26444,24 @@ void cpu_state_reset(CPUMIPSState *env) 
        env->CP0_Status |= (1 << CP0St_FR);

    }









    if (env->insn_flags & ISA_MIPS32R6) {









        /* PTW  =  1 */









        env->CP0_PWSize = 0x40;









        /* GDI  = 12 */









        /* UDI  = 12 */









        /* MDI  = 12 */









        /* PRI  = 12 */









        /* PTEI =  2 */









        env->CP0_PWField = 0x0C30C302;









    } else {









        /* GDI  =  0 */









        /* UDI  =  0 */









        /* MDI  =  0 */









        /* PRI  =  0 */









        /* PTEI =  2 */









        env->CP0_PWField = 0x02;









    }

















    if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {









        /*  microMIPS on reset when Config3.ISA is 3 */









        env->hflags |= MIPS_HFLAG_M16;