Commit 62f2b038 authored by Richard Henderson's avatar Richard Henderson
Browse files

target/openrisc: Add support for ORFPX64A32 



This is hardware support for double-precision floating-point using
pairs of 32-bit registers.  Fix latent bugs in the heretofore unused
helper_itofd and helper_ftoid.  Include the bit for cpu "any".
Change the default cpu for linux-user to "any".

Reviewed-by: default avatarStafford Horne <shorne@gmail.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent fe636d37

linux-user/openrisc/target_elf.h

+1 −1
Original line number Diff line number Diff line
@@ -9,6 +9,6 @@ 
#define OPENRISC_TARGET_ELF_H

static inline const char *cpu_get_model(uint32_t eflags)

{

    return "or1200";

    return "any";

}

#endif

target/openrisc/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -132,7 +132,7 @@ static void openrisc_any_initfn(Object *obj) 


    cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;

    cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |

                       CPUCFGR_AVRP | CPUCFGR_EVBARP;

                       CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S;



    /* 1Way, TLB_SIZE entries.  */

    cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))

target/openrisc/disas.c

+56 −0
Original line number Diff line number Diff line
@@ -166,3 +166,59 @@ FP_INSN(sfgt, s, "r%d, r%d", a->a, a->b) 
FP_INSN(sfge, s, "r%d, r%d", a->a, a->b)

FP_INSN(sflt, s, "r%d, r%d", a->a, a->b)

FP_INSN(sfle, s, "r%d, r%d", a->a, a->b)



FP_INSN(add, d,  "r%d,r%d, r%d,r%d, r%d,r%d",

        a->d, a->d + a->dp + 1,

        a->a, a->a + a->ap + 1,

        a->b, a->b + a->bp + 1)

FP_INSN(sub, d,  "r%d,r%d, r%d,r%d, r%d,r%d",

        a->d, a->d + a->dp + 1,

        a->a, a->a + a->ap + 1,

        a->b, a->b + a->bp + 1)

FP_INSN(mul, d,  "r%d,r%d, r%d,r%d, r%d,r%d",

        a->d, a->d + a->dp + 1,

        a->a, a->a + a->ap + 1,

        a->b, a->b + a->bp + 1)

FP_INSN(div, d,  "r%d,r%d, r%d,r%d, r%d,r%d",

        a->d, a->d + a->dp + 1,

        a->a, a->a + a->ap + 1,

        a->b, a->b + a->bp + 1)

FP_INSN(rem, d,  "r%d,r%d, r%d,r%d, r%d,r%d",

        a->d, a->d + a->dp + 1,

        a->a, a->a + a->ap + 1,

        a->b, a->b + a->bp + 1)

FP_INSN(madd, d, "r%d,r%d, r%d,r%d, r%d,r%d",

        a->d, a->d + a->dp + 1,

        a->a, a->a + a->ap + 1,

        a->b, a->b + a->bp + 1)



FP_INSN(itof, d, "r%d,r%d, r%d,r%d",

        a->d, a->d + a->dp + 1,

        a->a, a->a + a->ap + 1)

FP_INSN(ftoi, d, "r%d,r%d, r%d,r%d",

        a->d, a->d + a->dp + 1,

        a->a, a->a + a->ap + 1)



FP_INSN(stod, d, "r%d,r%d, r%d",

        a->d, a->d + a->dp + 1, a->a)

FP_INSN(dtos, d, "r%d r%d,r%d",

        a->d, a->a, a->a + a->ap + 1)



FP_INSN(sfeq, d, "r%d,r%d, r%d,r%d",

        a->a, a->a + a->ap + 1,

        a->b, a->b + a->bp + 1)

FP_INSN(sfne, d, "r%d,r%d, r%d,r%d",

        a->a, a->a + a->ap + 1,

        a->b, a->b + a->bp + 1)

FP_INSN(sfgt, d, "r%d,r%d, r%d,r%d",

        a->a, a->a + a->ap + 1,

        a->b, a->b + a->bp + 1)

FP_INSN(sfge, d, "r%d,r%d, r%d,r%d",

        a->a, a->a + a->ap + 1,

        a->b, a->b + a->bp + 1)

FP_INSN(sflt, d, "r%d,r%d, r%d,r%d",

        a->a, a->a + a->ap + 1,

        a->b, a->b + a->bp + 1)

FP_INSN(sfle, d, "r%d,r%d, r%d,r%d",

        a->a, a->a + a->ap + 1,

        a->b, a->b + a->bp + 1)

target/openrisc/fpu_helper.c

+12 −2
Original line number Diff line number Diff line
@@ -63,7 +63,7 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env) 


uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val)

{

    return int32_to_float64(val, &env->fp_status);

    return int64_to_float64(val, &env->fp_status);

}



uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val)
@@ -73,7 +73,7 @@ uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val) 


uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val)

{

    return float32_to_int64(val, &env->fp_status);

    return float64_to_int64_round_to_zero(val, &env->fp_status);

}



uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val)
@@ -81,6 +81,16 @@ uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val) 
    return float32_to_int32_round_to_zero(val, &env->fp_status);

}



uint64_t HELPER(stod)(CPUOpenRISCState *env, uint32_t val)

{

    return float32_to_float64(val, &env->fp_status);

}



uint32_t HELPER(dtos)(CPUOpenRISCState *env, uint64_t val)

{

    return float64_to_float32(val, &env->fp_status);

}



#define FLOAT_CALC(name)                                                  \

uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env,               \

                                     uint64_t fdt0, uint64_t fdt1)        \

target/openrisc/helper.h

+2 −0
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_RWG, i64, env, i64) 
DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_RWG, i32, env, i32)

DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_RWG, i64, env, i64)

DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_RWG, i32, env, i32)

DEF_HELPER_FLAGS_2(stod, TCG_CALL_NO_RWG, i64, env, i32)

DEF_HELPER_FLAGS_2(dtos, TCG_CALL_NO_RWG, i32, env, i64)



DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32)

DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)