Commit 62c34848 authored by Peter Maydell's avatar Peter Maydell
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180820' into staging 



target-arm queue:
 * Fix crash on conditional instruction in an IT block
 * docs/generic-loader: mention U-Boot and Intel HEX executable formats
 * hw/intc/arm_gicv3_its: downgrade error_report to warn_report in kvm_arm_its_reset
 * imx_serial: Generate interrupt on receive data ready if enabled
 * Fix various minor bugs in AArch32 Hyp related coprocessor registers
 * Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked)
 * Implement AArch32 ERET instruction
 * hw/arm/virt: Add virt-3.1 machine type
 * sdhci: add i.MX SD Stable Clock bit
 * Remove now-obsolete MMIO request_ptr APIs
 * hw/timer/m48t59: Move away from old_mmio accessors
 * hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module
 * nvic: Expose NMI line
 * hw/dma/pl080: cleanups and new features required for use in MPS boards

# gpg: Signature made Mon 20 Aug 2018 11:30:12 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180820: (25 commits)
  hw/dma/pl080: Remove hw_error() if DMA is enabled
  hw/dma/pl080: Correct bug in register address decode logic
  hw/dma/pl080: Provide device reset function
  hw/dma/pl080: Don't use CPU address space for DMA accesses
  hw/dma/pl080: Support all three interrupt lines
  hw/dma/pl080: Allow use as embedded-struct device
  nvic: Expose NMI line
  hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module
  hw/timer/m48t59: Move away from old_mmio accessors
  hw/misc: Remove mmio_interface device
  memory: Remove MMIO request_ptr APIs
  hw/ssi/xilinx_spips: Remove unneeded MMIO request_ptr code
  sdhci: add i.MX SD Stable Clock bit
  hw/arm/virt: Add virt-3.1 machine type
  target/arm: Implement AArch32 ERET instruction
  target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked)
  target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2
  target/arm: Implement AArch32 Hyp FARs
  target/arm: Implement AArch32 HVBAR
  target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefs
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 627fce61 b85fad15

MAINTAINERS

+3 −0
Original line number Diff line number Diff line
@@ -445,6 +445,7 @@ F: hw/char/pl011.c 
F: include/hw/char/pl011.h

F: hw/display/pl110*

F: hw/dma/pl080.c

F: include/hw/dma/pl080.h

F: hw/dma/pl330.c

F: hw/gpio/pl061.c

F: hw/input/pl050.c
@@ -456,6 +457,8 @@ F: hw/timer/cmsdk-apb-timer.c 
F: include/hw/timer/cmsdk-apb-timer.h

F: hw/char/cmsdk-apb-uart.c

F: include/hw/char/cmsdk-apb-uart.h

F: hw/watchdog/cmsdk-apb-watchdog.c

F: include/hw/watchdog/cmsdk-apb-watchdog.h

F: hw/misc/tz-ppc.c

F: include/hw/misc/tz-ppc.h

F: hw/misc/tz-mpc.c

Makefile.objs

+1 −0
Original line number Diff line number Diff line
@@ -240,6 +240,7 @@ trace-events-subdirs += hw/tpm 
trace-events-subdirs += hw/usb

trace-events-subdirs += hw/vfio

trace-events-subdirs += hw/virtio

trace-events-subdirs += hw/watchdog

trace-events-subdirs += hw/xen

trace-events-subdirs += io

trace-events-subdirs += linux-user

default-configs/arm-softmmu.mak

+1 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ CONFIG_STM32F205_SOC=y 


CONFIG_CMSDK_APB_TIMER=y

CONFIG_CMSDK_APB_UART=y

CONFIG_CMSDK_APB_WATCHDOG=y



CONFIG_MPS2_FPGAIO=y

CONFIG_MPS2_SCC=y

docs/generic-loader.txt

+10 −10
Original line number Diff line number Diff line
@@ -56,25 +56,25 @@ An example of setting CPU 0's PC to 0x8000 is: 


Loading Files

-------------

The loader device also allows files to be loaded into memory. It can load raw

files and ELF executable files.  Raw files are loaded verbatim.  ELF executable

files are loaded by an ELF loader.  The syntax is shown below:

The loader device also allows files to be loaded into memory. It can load ELF,

U-Boot, and Intel HEX executable formats as well as raw images.  The syntax is

shown below:



    -device loader,file=<file>[,addr=<addr>][,cpu-num=<cpu-num>][,force-raw=<raw>]



    <file>      - A file to be loaded into memory

    <addr>      - The addr in memory that the file should be loaded. This is

                  ignored if you are using an ELF (unless force-raw is true).

                  This is required if you aren't loading an ELF.

    <addr>      - The memory address where the file should be loaded. This is

                  required for raw images and ignored for non-raw files.

    <cpu-num>   - This specifies the CPU that should be used. This is an

                  optional argument and will cause the CPU's PC to be set to

                  where the image is stored or in the case of an ELF file to

                  the value in the header. This option should only be used

                  for the boot image.

                  the memory address where the raw file is loaded or the entry

                  point specified in the executable format header. This option

                  should only be used for the boot image.

                  This will also cause the image to be written to the specified

                  CPU's address space. If not specified, the default is CPU 0.

    <force-raw> - Setting force-raw=on forces the file to be treated as a raw

                  image.  This can be used to load ELF files as if they were raw.

                  image.  This can be used to load supported executable formats

                  as if they were raw.



All values are parsed using the standard QemuOps parsing. This allows the user

to specify any values in any format supported. By default the values

hw/arm/armv7m.c

+1 −0
Original line number Diff line number Diff line
@@ -202,6 +202,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp) 
     */

    qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);

    qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");

    qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI");



    /* Wire the NVIC up to the CPU */

    sbd = SYS_BUS_DEVICE(&s->nvic);