Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150518-3' into staging (62bf3df4) · Commits · SUMMER2020 / students / proj-2021291

default-configs/aarch64-softmmu.mak

+1 −1

Original line number	Diff line number	Diff line
		@@ -3,4 +3,4 @@
		# We support all the 32 bit boards so need all their config
		include arm-softmmu.mak

		# Currently no 64-bit specific config requirements
		CONFIG_XLNX_ZYNQMP=y

hw/arm/Makefile.objs

+1 −0

Original line number	Diff line number	Diff line
		@@ -10,3 +10,4 @@ obj-$(CONFIG_DIGIC) += digic.o
		obj-y += omap1.o omap2.o strongarm.o
		obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
		obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
		obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o

hw/arm/xlnx-ep108.c

0 → 100644

+82 −0

Original line number	Diff line number	Diff line
		/*
		* Xilinx ZynqMP EP108 board
		*
		* Copyright (C) 2015 Xilinx Inc
		* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of the GNU General Public License as published by the
		* Free Software Foundation; either version 2 of the License, or
		* (at your option) any later version.
		*
		* This program is distributed in the hope that it will be useful, but WITHOUT
		* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
		* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
		* for more details.
		*/

		#include "hw/arm/xlnx-zynqmp.h"
		#include "hw/boards.h"
		#include "qemu/error-report.h"
		#include "exec/address-spaces.h"

		typedef struct XlnxEP108 {
		XlnxZynqMPState soc;
		MemoryRegion ddr_ram;
		} XlnxEP108;

		/* Max 2GB RAM */
		#define EP108_MAX_RAM_SIZE 0x80000000ull

		static struct arm_boot_info xlnx_ep108_binfo;

		static void xlnx_ep108_init(MachineState *machine)
		{
		XlnxEP108 *s = g_new0(XlnxEP108, 1);
		Error *err = NULL;

		object_initialize(&s->soc, sizeof(s->soc), TYPE_XLNX_ZYNQMP);
		object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
		&error_abort);

		object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
		if (err) {
		error_report("%s", error_get_pretty(err));
		exit(1);
		}

		if (machine->ram_size > EP108_MAX_RAM_SIZE) {
		error_report("WARNING: RAM size " RAM_ADDR_FMT " above max supported, "
		"reduced to %llx", machine->ram_size, EP108_MAX_RAM_SIZE);
		machine->ram_size = EP108_MAX_RAM_SIZE;
		}

		if (machine->ram_size <= 0x08000000) {
		qemu_log("WARNING: RAM size " RAM_ADDR_FMT " is small for EP108",
		machine->ram_size);
		}

		memory_region_allocate_system_memory(&s->ddr_ram, NULL, "ddr-ram",
		machine->ram_size);
		memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);

		xlnx_ep108_binfo.ram_size = machine->ram_size;
		xlnx_ep108_binfo.kernel_filename = machine->kernel_filename;
		xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline;
		xlnx_ep108_binfo.initrd_filename = machine->initrd_filename;
		xlnx_ep108_binfo.loader_start = 0;
		arm_load_kernel(&s->soc.cpu[0], &xlnx_ep108_binfo);
		}

		static QEMUMachine xlnx_ep108_machine = {
		.name = "xlnx-ep108",
		.desc = "Xilinx ZynqMP EP108 board",
		.init = xlnx_ep108_init,
		};

		static void xlnx_ep108_machine_init(void)
		{
		qemu_register_machine(&xlnx_ep108_machine);
		}

		machine_init(xlnx_ep108_machine_init);

hw/arm/xlnx-zynqmp.c

0 → 100644

+211 −0

Original line number	Diff line number	Diff line
		/*
		* Xilinx Zynq MPSoC emulation
		*
		* Copyright (C) 2015 Xilinx Inc
		* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of the GNU General Public License as published by the
		* Free Software Foundation; either version 2 of the License, or
		* (at your option) any later version.
		*
		* This program is distributed in the hope that it will be useful, but WITHOUT
		* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
		* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
		* for more details.
		*/

		#include "hw/arm/xlnx-zynqmp.h"
		#include "hw/intc/arm_gic_common.h"
		#include "exec/address-spaces.h"

		#define GIC_NUM_SPI_INTR 160

		#define ARM_PHYS_TIMER_PPI 30
		#define ARM_VIRT_TIMER_PPI 27

		#define GIC_BASE_ADDR 0xf9000000
		#define GIC_DIST_ADDR 0xf9010000
		#define GIC_CPU_ADDR 0xf9020000

		static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
		0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
		};

		static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
		57, 59, 61, 63,
		};

		static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
		0xFF000000, 0xFF010000,
		};

		static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
		21, 22,
		};

		typedef struct XlnxZynqMPGICRegion {
		int region_index;
		uint32_t address;
		} XlnxZynqMPGICRegion;

		static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
		{ .region_index = 0, .address = GIC_DIST_ADDR, },
		{ .region_index = 1, .address = GIC_CPU_ADDR, },
		};

		static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
		{
		return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
		}

		static void xlnx_zynqmp_init(Object *obj)
		{
		XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
		int i;

		for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
		object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
		"cortex-a53-" TYPE_ARM_CPU);
		object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
		&error_abort);
		}

		object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
		qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());

		for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
		object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
		qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
		}

		for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
		object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
		qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
		}
		}

		static void xlnx_zynqmp_realize(DeviceState dev, Error *errp)
		{
		XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
		MemoryRegion *system_memory = get_system_memory();
		uint8_t i;
		qemu_irq gic_spi[GIC_NUM_SPI_INTR];
		Error *err = NULL;

		qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
		qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
		qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_CPUS);
		object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
		if (err) {
		error_propagate((errp), (err));
		return;
		}
		assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
		for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
		SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
		const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
		MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
		uint32_t addr = r->address;
		int j;

		sysbus_mmio_map(gic, r->region_index, addr);

		for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
		MemoryRegion *alias = &s->gic_mr[i][j];

		addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
		memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
		0, XLNX_ZYNQMP_GIC_REGION_SIZE);
		memory_region_add_subregion(system_memory, addr, alias);
		}
		}

		for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
		qemu_irq irq;

		object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
		"psci-conduit", &error_abort);
		if (i > 0) {
		/* Secondary CPUs start in PSCI powered-down state */
		object_property_set_bool(OBJECT(&s->cpu[i]), true,
		"start-powered-off", &error_abort);
		}

		object_property_set_int(OBJECT(&s->cpu[i]), GIC_BASE_ADDR,
		"reset-cbar", &err);
		if (err) {
		error_propagate((errp), (err));
		return;
		}

		object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
		if (err) {
		error_propagate((errp), (err));
		return;
		}

		sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
		qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
		irq = qdev_get_gpio_in(DEVICE(&s->gic),
		arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
		qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq);
		irq = qdev_get_gpio_in(DEVICE(&s->gic),
		arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
		qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq);
		}

		for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
		gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
		}

		for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
		NICInfo *nd = &nd_table[i];

		if (nd->used) {
		qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
		qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
		}
		object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
		if (err) {
		error_propagate((errp), (err));
		return;
		}
		sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
		sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
		gic_spi[gem_intr[i]]);
		}

		for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
		object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
		if (err) {
		error_propagate((errp), (err));
		return;
		}
		sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
		sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
		gic_spi[uart_intr[i]]);
		}
		}

		static void xlnx_zynqmp_class_init(ObjectClass oc, void data)
		{
		DeviceClass *dc = DEVICE_CLASS(oc);

		dc->realize = xlnx_zynqmp_realize;
		}

		static const TypeInfo xlnx_zynqmp_type_info = {
		.name = TYPE_XLNX_ZYNQMP,
		.parent = TYPE_DEVICE,
		.instance_size = sizeof(XlnxZynqMPState),
		.instance_init = xlnx_zynqmp_init,
		.class_init = xlnx_zynqmp_class_init,
		};

		static void xlnx_zynqmp_register_types(void)
		{
		type_register_static(&xlnx_zynqmp_type_info);
		}

		type_init(xlnx_zynqmp_register_types)

hw/char/cadence_uart.c

+47 −68

Original line number	Diff line number	Diff line
		@@ -16,9 +16,7 @@
		* with this program; if not, see <http://www.gnu.org/licenses/>.
		*/

		#include "hw/sysbus.h"
		#include "sysemu/char.h"
		#include "qemu/timer.h"
		#include "hw/char/cadence_uart.h"

		#ifdef CADENCE_UART_ERR_DEBUG
		#define DB_PRINT(...) do { \
		@@ -85,8 +83,6 @@
		#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
		#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)

		#define RX_FIFO_SIZE 16
		#define TX_FIFO_SIZE 16
		#define UART_INPUT_CLK 50000000

		#define R_CR (0x00/4)
		@@ -108,38 +104,18 @@
		#define R_PWID (0x40/4)
		#define R_TTRIG (0x44/4)

		#define R_MAX (R_TTRIG + 1)

		#define TYPE_CADENCE_UART "cadence_uart"
		#define CADENCE_UART(obj) OBJECT_CHECK(UartState, (obj), TYPE_CADENCE_UART)

		typedef struct {
		/< private >/
		SysBusDevice parent_obj;
		/< public >/

		MemoryRegion iomem;
		uint32_t r[R_MAX];
		uint8_t rx_fifo[RX_FIFO_SIZE];
		uint8_t tx_fifo[TX_FIFO_SIZE];
		uint32_t rx_wpos;
		uint32_t rx_count;
		uint32_t tx_count;
		uint64_t char_tx_time;
		CharDriverState *chr;
		qemu_irq irq;
		QEMUTimer *fifo_trigger_handle;
		} UartState;

		static void uart_update_status(UartState *s)

		static void uart_update_status(CadenceUARTState *s)
		{
		s->r[R_SR] = 0;

		s->r[R_SR] \|= s->rx_count == RX_FIFO_SIZE ? UART_SR_INTR_RFUL : 0;
		s->r[R_SR] \|= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
		: 0;
		s->r[R_SR] \|= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
		s->r[R_SR] \|= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;

		s->r[R_SR] \|= s->tx_count == TX_FIFO_SIZE ? UART_SR_INTR_TFUL : 0;
		s->r[R_SR] \|= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
		: 0;
		s->r[R_SR] \|= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
		s->r[R_SR] \|= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;

		@@ -150,14 +126,14 @@ static void uart_update_status(UartState *s)

		static void fifo_trigger_update(void *opaque)
		{
		UartState s = (UartState )opaque;
		CadenceUARTState *s = opaque;

		s->r[R_CISR] \|= UART_INTR_TIMEOUT;

		uart_update_status(s);
		}

		static void uart_rx_reset(UartState *s)
		static void uart_rx_reset(CadenceUARTState *s)
		{
		s->rx_wpos = 0;
		s->rx_count = 0;
		@@ -166,12 +142,12 @@ static void uart_rx_reset(UartState *s)
		}
		}

		static void uart_tx_reset(UartState *s)
		static void uart_tx_reset(CadenceUARTState *s)
		{
		s->tx_count = 0;
		}

		static void uart_send_breaks(UartState *s)
		static void uart_send_breaks(CadenceUARTState *s)
		{
		int break_enabled = 1;

		@@ -181,7 +157,7 @@ static void uart_send_breaks(UartState *s)
		}
		}

		static void uart_parameters_setup(UartState *s)
		static void uart_parameters_setup(CadenceUARTState *s)
		{
		QEMUSerialSetParams ssp;
		unsigned int baud_rate, packet_size;
		@@ -236,20 +212,20 @@ static void uart_parameters_setup(UartState *s)

		static int uart_can_receive(void *opaque)
		{
		UartState s = (UartState )opaque;
		int ret = MAX(RX_FIFO_SIZE, TX_FIFO_SIZE);
		CadenceUARTState *s = opaque;
		int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
		uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;

		if (ch_mode == NORMAL_MODE \|\| ch_mode == ECHO_MODE) {
		ret = MIN(ret, RX_FIFO_SIZE - s->rx_count);
		ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
		}
		if (ch_mode == REMOTE_LOOPBACK \|\| ch_mode == ECHO_MODE) {
		ret = MIN(ret, TX_FIFO_SIZE - s->tx_count);
		ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
		}
		return ret;
		}

		static void uart_ctrl_update(UartState *s)
		static void uart_ctrl_update(CadenceUARTState *s)
		{
		if (s->r[R_CR] & UART_CR_TXRST) {
		uart_tx_reset(s);
		@@ -268,7 +244,7 @@ static void uart_ctrl_update(UartState *s)

		static void uart_write_rx_fifo(void opaque, const uint8_t buf, int size)
		{
		UartState s = (UartState )opaque;
		CadenceUARTState *s = opaque;
		uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
		int i;

		@@ -276,12 +252,12 @@ static void uart_write_rx_fifo(void opaque, const uint8_t buf, int size)
		return;
		}

		if (s->rx_count == RX_FIFO_SIZE) {
		if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
		s->r[R_CISR] \|= UART_INTR_ROVR;
		} else {
		for (i = 0; i < size; i++) {
		s->rx_fifo[s->rx_wpos] = buf[i];
		s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
		s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
		s->rx_count++;
		}
		timer_mod(s->fifo_trigger_handle, new_rx_time +
		@@ -293,7 +269,7 @@ static void uart_write_rx_fifo(void opaque, const uint8_t buf, int size)
		static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
		void *opaque)
		{
		UartState *s = opaque;
		CadenceUARTState *s = opaque;
		int ret;

		/* instant drain the fifo when there's no back-end */
		@@ -320,14 +296,15 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
		return FALSE;
		}

		static void uart_write_tx_fifo(UartState s, const uint8_t buf, int size)
		static void uart_write_tx_fifo(CadenceUARTState s, const uint8_t buf,
		int size)
		{
		if ((s->r[R_CR] & UART_CR_TX_DIS) \|\| !(s->r[R_CR] & UART_CR_TX_EN)) {
		return;
		}

		if (size > TX_FIFO_SIZE - s->tx_count) {
		size = TX_FIFO_SIZE - s->tx_count;
		if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
		size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
		/*
		* This can only be a guest error via a bad tx fifo register push,
		* as can_receive() should stop remote loop and echo modes ever getting
		@@ -345,7 +322,7 @@ static void uart_write_tx_fifo(UartState s, const uint8_t buf, int size)

		static void uart_receive(void opaque, const uint8_t buf, int size)
		{
		UartState s = (UartState )opaque;
		CadenceUARTState *s = opaque;
		uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;

		if (ch_mode == NORMAL_MODE \|\| ch_mode == ECHO_MODE) {
		@@ -358,7 +335,7 @@ static void uart_receive(void opaque, const uint8_t buf, int size)

		static void uart_event(void *opaque, int event)
		{
		UartState s = (UartState )opaque;
		CadenceUARTState *s = opaque;
		uint8_t buf = '\0';

		if (event == CHR_EVENT_BREAK) {
		@@ -368,15 +345,15 @@ static void uart_event(void *opaque, int event)
		uart_update_status(s);
		}

		static void uart_read_rx_fifo(UartState s, uint32_t c)
		static void uart_read_rx_fifo(CadenceUARTState s, uint32_t c)
		{
		if ((s->r[R_CR] & UART_CR_RX_DIS) \|\| !(s->r[R_CR] & UART_CR_RX_EN)) {
		return;
		}

		if (s->rx_count) {
		uint32_t rx_rpos =
		(RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE;
		uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
		s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
		*c = s->rx_fifo[rx_rpos];
		s->rx_count--;

		@@ -393,7 +370,7 @@ static void uart_read_rx_fifo(UartState s, uint32_t c)
		static void uart_write(void *opaque, hwaddr offset,
		uint64_t value, unsigned size)
		{
		UartState s = (UartState )opaque;
		CadenceUARTState *s = opaque;

		DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
		offset >>= 2;
		@@ -437,11 +414,11 @@ static void uart_write(void *opaque, hwaddr offset,
		static uint64_t uart_read(void *opaque, hwaddr offset,
		unsigned size)
		{
		UartState s = (UartState )opaque;
		CadenceUARTState *s = opaque;
		uint32_t c = 0;

		offset >>= 2;
		if (offset >= R_MAX) {
		if (offset >= CADENCE_UART_R_MAX) {
		c = 0;
		} else if (offset == R_TX_RX) {
		uart_read_rx_fifo(s, &c);
		@@ -461,7 +438,7 @@ static const MemoryRegionOps uart_ops = {

		static void cadence_uart_reset(DeviceState *dev)
		{
		UartState *s = CADENCE_UART(dev);
		CadenceUARTState *s = CADENCE_UART(dev);

		s->r[R_CR] = 0x00000128;
		s->r[R_IMR] = 0;
		@@ -478,7 +455,7 @@ static void cadence_uart_reset(DeviceState *dev)

		static void cadence_uart_realize(DeviceState dev, Error *errp)
		{
		UartState *s = CADENCE_UART(dev);
		CadenceUARTState *s = CADENCE_UART(dev);

		s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
		fifo_trigger_update, s);
		@@ -495,7 +472,7 @@ static void cadence_uart_realize(DeviceState dev, Error *errp)
		static void cadence_uart_init(Object *obj)
		{
		SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
		UartState *s = CADENCE_UART(obj);
		CadenceUARTState *s = CADENCE_UART(obj);

		memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
		sysbus_init_mmio(sbd, &s->iomem);
		@@ -506,7 +483,7 @@ static void cadence_uart_init(Object *obj)

		static int cadence_uart_post_load(void *opaque, int version_id)
		{
		UartState *s = opaque;
		CadenceUARTState *s = opaque;

		uart_parameters_setup(s);
		uart_update_status(s);
		@@ -519,13 +496,15 @@ static const VMStateDescription vmstate_cadence_uart = {
		.minimum_version_id = 2,
		.post_load = cadence_uart_post_load,
		.fields = (VMStateField[]) {
		VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
		VMSTATE_UINT8_ARRAY(rx_fifo, UartState, RX_FIFO_SIZE),
		VMSTATE_UINT8_ARRAY(tx_fifo, UartState, RX_FIFO_SIZE),
		VMSTATE_UINT32(rx_count, UartState),
		VMSTATE_UINT32(tx_count, UartState),
		VMSTATE_UINT32(rx_wpos, UartState),
		VMSTATE_TIMER_PTR(fifo_trigger_handle, UartState),
		VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
		VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
		CADENCE_UART_RX_FIFO_SIZE),
		VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
		CADENCE_UART_TX_FIFO_SIZE),
		VMSTATE_UINT32(rx_count, CadenceUARTState),
		VMSTATE_UINT32(tx_count, CadenceUARTState),
		VMSTATE_UINT32(rx_wpos, CadenceUARTState),
		VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
		VMSTATE_END_OF_LIST()
		}
		};
		@@ -544,7 +523,7 @@ static void cadence_uart_class_init(ObjectClass klass, void data)
		static const TypeInfo cadence_uart_info = {
		.name = TYPE_CADENCE_UART,
		.parent = TYPE_SYS_BUS_DEVICE,
		.instance_size = sizeof(UartState),
		.instance_size = sizeof(CadenceUARTState),
		.instance_init = cadence_uart_init,
		.class_init = cadence_uart_class_init,
		};