Commit 629fcaa7 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Convert T16, Conditional branches, Supervisor call 



Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-63-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 564b125f

target/arm/t16.decode

+12 −0
Original line number Diff line number Diff line
@@ -28,11 +28,13 @@ 
&rr              !extern rd rm

&ri              !extern rd imm

&r               !extern rm

&i               !extern imm

&ldst_rr         !extern p w u rn rt rm shimm shtype

&ldst_ri         !extern p w u rn rt imm

&ldst_block      !extern rn i b u w list

&setend          !extern E

&cps             !extern mode imod M A I F

&ci              !extern cond imm



# Set S if the instruction is outside of an IT block.

%s               !function=t16_setflags
@@ -231,3 +233,13 @@ STM 1011 010 ......... \ 
                &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list

LDM_t16         1011 110 ......... \

                &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list



# Conditional branches, Supervisor call



%imm8_0x2       0:s8 !function=times_2



{

  UDF           1101 1110 ---- ----

  SVC           1101 1111 imm:8                 &i

  B_cond_thumb  1101 cond:4 ........            &ci imm=%imm8_0x2

}

target/arm/translate.c

+3 −23
Original line number Diff line number Diff line
@@ -10721,7 +10721,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) 


static void disas_thumb_insn(DisasContext *s, uint32_t insn)

{

    uint32_t val, op, rm, rd, shift, cond;

    uint32_t val, op, rm, rd, shift;

    int32_t offset;

    TCGv_i32 tmp;

    TCGv_i32 tmp2;
@@ -10860,28 +10860,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) 
        }

        break;



    case 13:

        /* conditional branch or swi */

        cond = (insn >> 8) & 0xf;

        if (cond == 0xe)

            goto undef;



        if (cond == 0xf) {

            /* swi */

            gen_set_pc_im(s, s->base.pc_next);

            s->svc_imm = extract32(insn, 0, 8);

            s->base.is_jmp = DISAS_SWI;

            break;

        }

        /* generate a conditional jump to next instruction */

        arm_skip_unless(s, cond);



        /* jump to the offset */

        val = read_pc(s);

        offset = ((int32_t)insn << 24) >> 24;

        val += offset << 1;

        gen_jmp(s, val);

        break;

    case 13: /* conditional branch or swi, in decodetree */

        goto illegal_op;



    case 14:

        if (insn & (1 << 11)) {