Commit 62955e10 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging 



Miscellaneous bugfixes

# gpg: Signature made Wed 15 Nov 2017 15:27:25 GMT
# gpg:                using RSA key 0xBFFBD25F78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>"
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream:
  fix scripts/update-linux-headers.sh here document
  exec: Do not resolve subpage in mru_section
  util/stats64: Fix min/max comparisons
  cpu-exec: avoid cpu_exec_nocache infinite loop with record/replay
  cpu-exec: don't overwrite exception_index
  vhost-user-scsi: add missing virtqueue_size param
  target-i386: adds PV_TLB_FLUSH CPUID feature bit
  thread-posix: fix qemu_rec_mutex_trylock macro
  Makefile: simpler/faster "make help"
  ioapic/tracing: Remove last DPRINTFs
  Enable 8-byte wide MMIO for 16550 serial devices

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 6a7cb8c3 4950b1a7

Makefile

+1 −1
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ BUILD_DIR=$(CURDIR) 
# Before including a proper config-host.mak, assume we are in the source tree

SRC_PATH=.



UNCHECKED_GOALS := %clean TAGS cscope ctags docker docker-%

UNCHECKED_GOALS := %clean TAGS cscope ctags docker docker-% help



# All following code might depend on configuration variables

ifneq ($(wildcard config-host.mak),)

accel/tcg/cpu-exec.c

+57 −42
Original line number Diff line number Diff line
@@ -470,7 +470,19 @@ static inline void cpu_handle_debug_exception(CPUState *cpu) 


static inline bool cpu_handle_exception(CPUState *cpu, int *ret)

{

    if (cpu->exception_index >= 0) {

    if (cpu->exception_index < 0) {

#ifndef CONFIG_USER_ONLY

        if (replay_has_exception()

               && cpu->icount_decr.u16.low + cpu->icount_extra == 0) {

            /* try to cause an exception pending in the log */

            cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()), true);

        }

#endif

        if (cpu->exception_index < 0) {

            return false;

        }

    }



    if (cpu->exception_index >= EXCP_INTERRUPT) {

        /* exit request from the cpu execution loop */

        *ret = cpu->exception_index;
@@ -503,15 +515,6 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) 
            *ret = EXCP_INTERRUPT;

            return true;

        }

#endif

        }

#ifndef CONFIG_USER_ONLY

    } else if (replay_has_exception()

               && cpu->icount_decr.u16.low + cpu->icount_extra == 0) {

        /* try to cause an exception pending in the log */

        cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()), true);

        *ret = -1;

        return true;

#endif

    }
@@ -522,6 +525,19 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, 
                                        TranslationBlock **last_tb)

{

    CPUClass *cc = CPU_GET_CLASS(cpu);

    int32_t insns_left;



    /* Clear the interrupt flag now since we're processing

     * cpu->interrupt_request and cpu->exit_request.

     */

    insns_left = atomic_read(&cpu->icount_decr.u32);

    atomic_set(&cpu->icount_decr.u16.high, 0);

    if (unlikely(insns_left < 0)) {

        /* Ensure the zeroing of icount_decr comes before the next read

         * of cpu->exit_request or cpu->interrupt_request.

         */

        smp_mb();

    }



    if (unlikely(atomic_read(&cpu->interrupt_request))) {

        int interrupt_request;
@@ -594,7 +610,9 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, 
    if (unlikely(atomic_read(&cpu->exit_request)

        || (use_icount && cpu->icount_decr.u16.low + cpu->icount_extra == 0))) {

        atomic_set(&cpu->exit_request, 0);

        if (cpu->exception_index == -1) {

            cpu->exception_index = EXCP_INTERRUPT;

        }

        return true;

    }
@@ -618,17 +636,14 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, 


    *last_tb = NULL;

    insns_left = atomic_read(&cpu->icount_decr.u32);

    atomic_set(&cpu->icount_decr.u16.high, 0);

    if (insns_left < 0) {

        /* Something asked us to stop executing chained TBs; just

         * continue round the main loop. Whatever requested the exit

         * will also have set something else (eg exit_request or

         * interrupt_request) which we will handle next time around

         * the loop.  But we need to ensure the zeroing of icount_decr

         * comes before the next read of cpu->exit_request

         * or cpu->interrupt_request.

         * interrupt_request) which will be handled by

         * cpu_handle_interrupt.  cpu_handle_interrupt will also

         * clear cpu->icount_decr.u16.high.

         */

        smp_mb();

        return;

    }

exec.c

+3 −9
Original line number Diff line number Diff line
@@ -410,22 +410,16 @@ static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d, 
{

    MemoryRegionSection *section = atomic_read(&d->mru_section);

    subpage_t *subpage;

    bool update;



    if (section && section != &d->map.sections[PHYS_SECTION_UNASSIGNED] &&

        section_covers_addr(section, addr)) {

        update = false;

    } else {

    if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||

        !section_covers_addr(section, addr)) {

        section = phys_page_find(d, addr);

        update = true;

        atomic_set(&d->mru_section, section);

    }

    if (resolve_subpage && section->mr->subpage) {

        subpage = container_of(section->mr, subpage_t, iomem);

        section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];

    }

    if (update) {

        atomic_set(&d->mru_section, section);

    }

    return section;

}

hw/char/serial.c

+7 −1
Original line number Diff line number Diff line
@@ -1005,7 +1005,7 @@ static void serial_mm_write(void *opaque, hwaddr addr, 
                            uint64_t value, unsigned size)

{

    SerialState *s = opaque;

    value &= ~0u >> (32 - (size * 8));

    value &= 255;

    serial_ioport_write(s, addr >> s->it_shift, value, 1);

}
@@ -1014,16 +1014,22 @@ static const MemoryRegionOps serial_mm_ops[3] = { 
        .read = serial_mm_read,

        .write = serial_mm_write,

        .endianness = DEVICE_NATIVE_ENDIAN,

        .valid.max_access_size = 8,

        .impl.max_access_size = 8,

    },

    [DEVICE_LITTLE_ENDIAN] = {

        .read = serial_mm_read,

        .write = serial_mm_write,

        .endianness = DEVICE_LITTLE_ENDIAN,

        .valid.max_access_size = 8,

        .impl.max_access_size = 8,

    },

    [DEVICE_BIG_ENDIAN] = {

        .read = serial_mm_read,

        .write = serial_mm_write,

        .endianness = DEVICE_BIG_ENDIAN,

        .valid.max_access_size = 8,

        .impl.max_access_size = 8,

    },

};

hw/intc/ioapic.c

+3 −14
Original line number Diff line number Diff line
@@ -35,15 +35,6 @@ 
#include "hw/i386/x86-iommu.h"

#include "trace.h"



//#define DEBUG_IOAPIC



#ifdef DEBUG_IOAPIC

#define DPRINTF(fmt, ...)                                       \

    do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)

#else

#define DPRINTF(fmt, ...)

#endif



#define APIC_DELIVERY_MODE_SHIFT 8

#define APIC_POLARITY_SHIFT 14

#define APIC_TRIG_MODE_SHIFT 15
@@ -157,7 +148,7 @@ static void ioapic_set_irq(void *opaque, int vector, int level) 
     * to GSI 2.  GSI maps to ioapic 1-1.  This is not

     * the cleanest way of doing it but it should work. */



    DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);

    trace_ioapic_set_irq(vector, level);

    if (vector == 0) {

        vector = 2;

    }
@@ -290,11 +281,10 @@ ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size) 
                }

            }

        }

        DPRINTF("read: %08x = %08x\n", s->ioregsel, val);

        break;

    }



    trace_ioapic_mem_read(addr, size, val);

    trace_ioapic_mem_read(addr, s->ioregsel, size, val);



    return val;

}
@@ -335,7 +325,7 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, 
    int index;



    addr &= 0xff;

    trace_ioapic_mem_write(addr, size, val);

    trace_ioapic_mem_write(addr, s->ioregsel, size, val);



    switch (addr) {

    case IOAPIC_IOREGSEL:
@@ -345,7 +335,6 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, 
        if (size != 4) {

            break;

        }

        DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val);

        switch (s->ioregsel) {

        case IOAPIC_REG_ID:

            s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;