Commit 625fa8de authored by Peter Maydell's avatar Peter Maydell
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Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20190108' into staging 



Queued target/alpha patches

# gpg: Signature made Tue 08 Jan 2019 02:14:18 GMT
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-axp-20190108:
  pc-bios: Update palcode-clipper
  target/alpha: Fix user-only initialization of fpcr
  hw/alpha/typhoon: Stop calling cpu_unassigned_access()

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents c102d947 ac89de40

hw/alpha/typhoon.c

+27 −20
Original line number Diff line number Diff line
@@ -75,7 +75,9 @@ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) 
    }

}



static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)

static MemTxResult cchip_read(void *opaque, hwaddr addr,

                              uint64_t *data, unsigned size,

                              MemTxAttrs attrs)

{

    CPUState *cpu = current_cpu;

    TyphoonState *s = opaque;
@@ -196,11 +198,11 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) 
        break;



    default:

        cpu_unassigned_access(cpu, addr, false, false, 0, size);

        return -1;

        return MEMTX_ERROR;

    }



    return ret;

    *data = ret;

    return MEMTX_OK;

}



static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size)
@@ -209,7 +211,8 @@ static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size) 
    return 0;

}



static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)

static MemTxResult pchip_read(void *opaque, hwaddr addr, uint64_t *data,

                              unsigned size, MemTxAttrs attrs)

{

    TyphoonState *s = opaque;

    uint64_t ret = 0;
@@ -294,15 +297,16 @@ static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) 
        break;



    default:

        cpu_unassigned_access(current_cpu, addr, false, false, 0, size);

        return -1;

        return MEMTX_ERROR;

    }



    return ret;

    *data = ret;

    return MEMTX_OK;

}



static void cchip_write(void *opaque, hwaddr addr,

                        uint64_t val, unsigned size)

static MemTxResult cchip_write(void *opaque, hwaddr addr,

                               uint64_t val, unsigned size,

                               MemTxAttrs attrs)

{

    TyphoonState *s = opaque;

    uint64_t oldval, newval;
@@ -446,9 +450,10 @@ static void cchip_write(void *opaque, hwaddr addr, 
        break;



    default:

        cpu_unassigned_access(current_cpu, addr, true, false, 0, size);

        return;

        return MEMTX_ERROR;

    }



    return MEMTX_OK;

}



static void dchip_write(void *opaque, hwaddr addr,
@@ -457,8 +462,9 @@ static void dchip_write(void *opaque, hwaddr addr, 
    /* Skip this.  It's all related to DRAM timing and setup.  */

}



static void pchip_write(void *opaque, hwaddr addr,

                        uint64_t val, unsigned size)

static MemTxResult pchip_write(void *opaque, hwaddr addr,

                               uint64_t val, unsigned size,

                               MemTxAttrs attrs)

{

    TyphoonState *s = opaque;

    uint64_t oldval;
@@ -553,14 +559,15 @@ static void pchip_write(void *opaque, hwaddr addr, 
        break;



    default:

        cpu_unassigned_access(current_cpu, addr, true, false, 0, size);

        return;

        return MEMTX_ERROR;

    }



    return MEMTX_OK;

}



static const MemoryRegionOps cchip_ops = {

    .read = cchip_read,

    .write = cchip_write,

    .read_with_attrs = cchip_read,

    .write_with_attrs = cchip_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

    .valid = {

        .min_access_size = 8,
@@ -587,8 +594,8 @@ static const MemoryRegionOps dchip_ops = { 
};



static const MemoryRegionOps pchip_ops = {

    .read = pchip_read,

    .write = pchip_write,

    .read_with_attrs = pchip_read,

    .write_with_attrs = pchip_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

    .valid = {

        .min_access_size = 8,

pc-bios/palcode-clipper

+3.21 KiB (152 KiB)

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qemu-palcode @ 51c237d7

Original line number Diff line number Diff line 
Subproject commit f3c7e44c70254975df2a00af39701eafbac4d471
 
Subproject commit 51c237d7e20d05100eacadee2f61abc17e6bc097

target/alpha/cpu.c

+3 −3
Original line number Diff line number Diff line
@@ -205,9 +205,9 @@ static void alpha_cpu_initfn(Object *obj) 
    env->lock_addr = -1;

#if defined(CONFIG_USER_ONLY)

    env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;

    cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD

    cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD

                                         | FPCR_UNFD | FPCR_INED | FPCR_DNOD

                               | FPCR_DYN_NORMAL));

                                         | FPCR_DYN_NORMAL) << 32);

#else

    env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN;

#endif