Commit 623e250a authored by Tom Musta's avatar Tom Musta Committed by Alexander Graf
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linux-user: Correct AUXV Cache Line Sizes for PowerPC 



Set the AT_ICACHEBSIZE and AT_DCACHEBSIZE entries of the AUXV to match the
CPU model's cache line sizes.  This fixes memory clobbering problems on more
recent Book 3s implementations; memset(p, 0, N) will use the dcbz instruction
when N is sufficiently large and many of the newer server CPUs have cache lines
sizes of 128 bytes.

Signed-off-by: default avatarTom Musta <tommusta@gmail.com>
Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
parent ff4873cb

linux-user/elfload.c

+3 −2
Original line number Diff line number Diff line
@@ -774,8 +774,9 @@ static uint32_t get_elf_hwcap(void) 
#define DLINFO_ARCH_ITEMS       5

#define ARCH_DLINFO                                     \

    do {                                                \

        NEW_AUX_ENT(AT_DCACHEBSIZE, 0x20);              \

        NEW_AUX_ENT(AT_ICACHEBSIZE, 0x20);              \

        PowerPCCPU *cpu = POWERPC_CPU(thread_cpu);              \

        NEW_AUX_ENT(AT_DCACHEBSIZE, cpu->env.dcache_line_size); \

        NEW_AUX_ENT(AT_ICACHEBSIZE, cpu->env.icache_line_size); \

        NEW_AUX_ENT(AT_UCACHEBSIZE, 0);                 \

        /*                                              \

         * Now handle glibc compatibility.              \