Commit 621c1006 authored by Bin Meng's avatar Bin Meng Committed by Alistair Francis
Browse files

hw/riscv: sifive_gpio: Do not blindly trigger output IRQs 



At present the GPIO output IRQs are triggered each time any GPIO
register is written. However this is not correct. We should only
trigger the output IRQ when the pin is configured as output enable.

Signed-off-by: default avatarBin Meng <bin.meng@windriver.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-9-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
parent 8a88b9f5

hw/riscv/sifive_gpio.c

+3 −1
Original line number Diff line number Diff line
@@ -76,7 +76,9 @@ static void update_state(SIFIVEGPIOState *s) 
            actual_value = pull;

        }



        if (output_en) {

            qemu_set_irq(s->output[i], actual_value);

        }



        /* Input value */

        ival = input_en && actual_value;