Unverified Commit 62045535 authored by Kito Cheng's avatar Kito Cheng Committed by Palmer Dabbelt
Browse files

target/riscv: Fix wrong expanding for c.fswsp 



base register is no rs1 not rs2 for fsw.

Signed-off-by: default avatarKito Cheng <kito.cheng@gmail.com>
Reviewed-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 4aef5196

target/riscv/insn_trans/trans_rvc.inc.c

+1 −1
Original line number Diff line number Diff line
@@ -337,7 +337,7 @@ static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) 
{

#ifdef TARGET_RISCV32

    /* C.FSWSP */

    arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp };

    arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };

    return trans_fsw(ctx, &a_fsw);

#else

    /* C.SDSP */