Commit 61126a8b authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging 



x86 queue, 2018-05-15

* KnightsMill CPU model
* CLDEMOTE(Demote Cache Line) cpu feature
* pc-i440fx-2.13 and pc-q35-2.13 machine-types
* Add model-specific cache information to EPYC CPU model

# gpg: Signature made Tue 15 May 2018 22:53:12 BST
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-next-pull-request:
  i386: Add new property to control cache info
  pc: add 2.13 machine types
  i386: Initialize cache information for EPYC family processors
  i386: Add cache information in X86CPUDefinition
  i386: Helpers to encode cache information consistently
  x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature
  i386: add KnightsMill cpu model

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents c416eece ab8f992e

hw/i386/pc_piix.c

+12 −3
Original line number Diff line number Diff line
@@ -425,21 +425,30 @@ static void pc_i440fx_machine_options(MachineClass *m) 
    m->default_display = "std";

}



static void pc_i440fx_2_12_machine_options(MachineClass *m)

static void pc_i440fx_2_13_machine_options(MachineClass *m)

{

    pc_i440fx_machine_options(m);

    m->alias = "pc";

    m->is_default = 1;

}



DEFINE_I440FX_MACHINE(v2_13, "pc-i440fx-2.13", NULL,

                      pc_i440fx_2_13_machine_options);



static void pc_i440fx_2_12_machine_options(MachineClass *m)

{

    pc_i440fx_2_13_machine_options(m);

    m->is_default = 0;

    m->alias = NULL;

    SET_MACHINE_COMPAT(m, PC_COMPAT_2_12);

}



DEFINE_I440FX_MACHINE(v2_12, "pc-i440fx-2.12", NULL,

                      pc_i440fx_2_12_machine_options);



static void pc_i440fx_2_11_machine_options(MachineClass *m)

{

    pc_i440fx_2_12_machine_options(m);

    m->is_default = 0;

    m->alias = NULL;

    SET_MACHINE_COMPAT(m, PC_COMPAT_2_11);

}

hw/i386/pc_q35.c

+11 −2
Original line number Diff line number Diff line
@@ -308,12 +308,22 @@ static void pc_q35_machine_options(MachineClass *m) 
    m->max_cpus = 288;

}



static void pc_q35_2_12_machine_options(MachineClass *m)

static void pc_q35_2_13_machine_options(MachineClass *m)

{

    pc_q35_machine_options(m);

    m->alias = "q35";

}



DEFINE_Q35_MACHINE(v2_13, "pc-q35-2.13", NULL,

                    pc_q35_2_13_machine_options);



static void pc_q35_2_12_machine_options(MachineClass *m)

{

    pc_q35_2_13_machine_options(m);

    m->alias = NULL;

    SET_MACHINE_COMPAT(m, PC_COMPAT_2_12);

}



DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,

                   pc_q35_2_12_machine_options);
@@ -323,7 +333,6 @@ static void pc_q35_2_11_machine_options(MachineClass *m) 


    pc_q35_2_12_machine_options(m);

    pcmc->default_nic_model = "e1000";

    m->alias = NULL;

    SET_MACHINE_COMPAT(m, PC_COMPAT_2_11);

}

include/hw/i386/pc.h

+8 −0
Original line number Diff line number Diff line
@@ -296,6 +296,14 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t); 
int e820_get_num_entries(void);

bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);



#define PC_COMPAT_2_12 \

    HW_COMPAT_2_12 \

    {\

        .driver   = TYPE_X86_CPU,\

        .property = "legacy-cache",\

        .value    = "on",\

    },



#define PC_COMPAT_2_11 \

    HW_COMPAT_2_11 \

    {\

target/i386/cpu.c

+511 −124

File changed.

Preview size limit exceeded, changes collapsed.

target/i386/cpu.h

+66 −0
Original line number Diff line number Diff line
@@ -680,6 +680,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 
#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */

#define CPUID_7_0_ECX_LA57     (1U << 16)

#define CPUID_7_0_ECX_RDPID    (1U << 22)

#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)  /* CLDEMOTE Instruction */



#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */

#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
@@ -1044,6 +1045,65 @@ typedef enum TPRAccess { 
    TPR_ACCESS_WRITE,

} TPRAccess;



/* Cache information data structures: */



enum CacheType {

    DCACHE,

    ICACHE,

    UNIFIED_CACHE

};



typedef struct CPUCacheInfo {

    enum CacheType type;

    uint8_t level;

    /* Size in bytes */

    uint32_t size;

    /* Line size, in bytes */

    uint16_t line_size;

    /*

     * Associativity.

     * Note: representation of fully-associative caches is not implemented

     */

    uint8_t associativity;

    /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */

    uint8_t partitions;

    /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */

    uint32_t sets;

    /*

     * Lines per tag.

     * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].

     * (Is this synonym to @partitions?)

     */

    uint8_t lines_per_tag;



    /* Self-initializing cache */

    bool self_init;

    /*

     * WBINVD/INVD is not guaranteed to act upon lower level caches of

     * non-originating threads sharing this cache.

     * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]

     */

    bool no_invd_sharing;

    /*

     * Cache is inclusive of lower cache levels.

     * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].

     */

    bool inclusive;

    /*

     * A complex function is used to index the cache, potentially using all

     * address bits.  CPUID[4].EDX[bit 2].

     */

    bool complex_indexing;

} CPUCacheInfo;





typedef struct CPUCaches {

        CPUCacheInfo l1d_cache;

        CPUCacheInfo l1i_cache;

        CPUCacheInfo l2_cache;

        CPUCacheInfo l3_cache;

} CPUCaches;



typedef struct CPUX86State {

    /* standard registers */

    target_ulong regs[CPU_NB_REGS];
@@ -1232,6 +1292,7 @@ typedef struct CPUX86State { 
    /* Features that were explicitly enabled/disabled */

    FeatureWordArray user_features;

    uint32_t cpuid_model[12];

    CPUCaches *cache_info;



    /* MTRRs */

    uint64_t mtrr_fixed[11];
@@ -1338,6 +1399,11 @@ struct X86CPU { 
     */

    bool enable_l3_cache;



    /* Compatibility bits for old machine types.

     * If true present the old cache topology information

     */

    bool legacy_cache;



    /* Compatibility bits for old machine types: */

    bool enable_cpuid_0xb;