Commit 60905286 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.1-20190529' into staging 



ppc patch queue 2019-05-29

Next pull request against qemu-4.1.  Highlights:
  * KVM accelerated support for the XIVE interrupt controller in PAPR
    guests
  * A number of TCG vector fixes
  * Fixes for the PReP / 40p machine
  * Improvements to make check-tcg test coverage

Other than that it's just a bunch of assorted fixes, cleanups and
minor improvements.

This supersedes both the pull request dated 2019-05-21 and the one
dated 2019-05-22.  I've dropped one hunk which I think may have caused
the check-tcg failure that Peter saw (by enabling the ppc64abi32
build, which I think has been broken for ages).  I'm not entirely
certain, since I haven't reproduced exactly the same failure.

# gpg: Signature made Wed 29 May 2019 07:49:04 BST
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-4.1-20190529: (44 commits)
  ppc/pnv: add dummy XSCOM registers for PRD initialization
  ppc/pnv: introduce new skiboot platform properties
  spapr: Don't migrate the hpt_maxpagesize cap to older machine types
  spapr: change default interrupt mode to 'dual'
  spapr/xive: fix multiple resets when using the 'dual' interrupt mode
  docs: provide documentation on the POWER9 XIVE interrupt controller
  spapr/irq: add KVM support to the 'dual' machine
  ppc/xics: fix irq priority in ics_set_irq_type()
  spapr/irq: initialize the IRQ device only once
  spapr/irq: introduce a spapr_irq_init_device() helper
  spapr: check for the activation of the KVM IRQ device
  spapr: introduce routines to delete the KVM IRQ device
  sysbus: add a sysbus_mmio_unmap() helper
  spapr/xive: activate KVM support
  spapr/xive: add migration support for KVM
  spapr/xive: introduce a VM state change handler
  spapr/xive: add state synchronization with KVM
  spapr/xive: add hcall support when under KVM
  spapr/xive: add KVM support
  spapr: Print out extra hints when CAS negotiation of interrupt mode fails
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 48a8b399 ce4b1b56

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -1720,6 +1720,7 @@ L: qemu-ppc@nongnu.org 
S: Supported

F: hw/*/*xive*

F: include/hw/*/*xive*

F: docs/*/*xive*



Subsystems

----------

configure

+31 −18
Original line number Diff line number Diff line
@@ -198,7 +198,7 @@ supported_kvm_target() { 
        i386:i386 | i386:x86_64 | i386:x32 | \

        x86_64:i386 | x86_64:x86_64 | x86_64:x32 | \

        mips:mips | mipsel:mips | \

        ppc:ppc | ppc64:ppc | ppc:ppc64 | ppc64:ppc64 | \

        ppc:ppc | ppc64:ppc | ppc:ppc64 | ppc64:ppc64 | ppc64:ppc64le | \

        s390x:s390x)

            return 0

        ;;
@@ -502,8 +502,11 @@ cross_cc_arm="arm-linux-gnueabihf-gcc" 
cross_cc_cflags_armeb="-mbig-endian"

cross_cc_i386="i386-pc-linux-gnu-gcc"

cross_cc_cflags_i386=""

cross_cc_powerpc="powerpc-linux-gnu-gcc"

cross_cc_powerpc="powerpc-linux-gnu-gcc"

cross_cc_ppc="powerpc-linux-gnu-gcc"

cross_cc_cflags_ppc="-m32"

cross_cc_ppc64="powerpc-linux-gnu-gcc"

cross_cc_cflags_ppc64="-m64"

cross_cc_ppc64le="powerpc64le-linux-gnu-gcc"



enabled_cross_compilers=""
@@ -700,7 +703,11 @@ elif check_define __sparc__ ; then 
  fi

elif check_define _ARCH_PPC ; then

  if check_define _ARCH_PPC64 ; then

    if check_define _LITTLE_ENDIAN ; then

      cpu="ppc64le"

    else

      cpu="ppc64"

    fi

  else

    cpu="ppc"

  fi
@@ -731,10 +738,14 @@ ARCH= 
# Note that this case should only have supported host CPUs, not guests.

case "$cpu" in

  ppc|ppc64|s390|s390x|sparc64|x32|riscv32|riscv64)

    cpu="$cpu"

    supported_cpu="yes"

    eval "cross_cc_${cpu}=\$host_cc"

  ;;

  ppc64le)

    ARCH="ppc64"

    supported_cpu="yes"

    cross_cc_ppc64le=$host_cc

  ;;

  i386|i486|i586|i686|i86pc|BePC)

    cpu="i386"

    supported_cpu="yes"
@@ -1538,44 +1549,44 @@ case "$cpu" in 
    ppc)

           CPU_CFLAGS="-m32"

           LDFLAGS="-m32 $LDFLAGS"

           cross_cc_powerpc=$cc

           cross_cc_cflags_powerpc=$CPU_CFLAGS

           cross_cc_ppc=$cc

           cross_cc_cflags_ppc="$CPU_CFLAGS"

           ;;

    ppc64)

           CPU_CFLAGS="-m64"

           LDFLAGS="-m64 $LDFLAGS"

           cross_cc_ppc64=$cc

           cross_cc_cflags_ppc64=$CPU_CFLAGS

           cross_cc_cflags_ppc64="$CPU_CFLAGS"

           ;;

    sparc)

           CPU_CFLAGS="-m32 -mv8plus -mcpu=ultrasparc"

           LDFLAGS="-m32 -mv8plus $LDFLAGS"

           cross_cc_sparc=$cc

           cross_cc_cflags_sparc=$CPU_CFLAGS

           cross_cc_cflags_sparc="$CPU_CFLAGS"

           ;;

    sparc64)

           CPU_CFLAGS="-m64 -mcpu=ultrasparc"

           LDFLAGS="-m64 $LDFLAGS"

           cross_cc_sparc64=$cc

           cross_cc_cflags_sparc64=$CPU_CFLAGS

           cross_cc_cflags_sparc64="$CPU_CFLAGS"

           ;;

    s390)

           CPU_CFLAGS="-m31"

           LDFLAGS="-m31 $LDFLAGS"

           cross_cc_s390=$cc

           cross_cc_cflags_s390=$CPU_CFLAGS

           cross_cc_cflags_s390="$CPU_CFLAGS"

           ;;

    s390x)

           CPU_CFLAGS="-m64"

           LDFLAGS="-m64 $LDFLAGS"

           cross_cc_s390x=$cc

           cross_cc_cflags_s390x=$CPU_CFLAGS

           cross_cc_cflags_s390x="$CPU_CFLAGS"

           ;;

    i386)

           CPU_CFLAGS="-m32"

           LDFLAGS="-m32 $LDFLAGS"

           cross_cc_i386=$cc

           cross_cc_cflags_i386=$CPU_CFLAGS

           cross_cc_cflags_i386="$CPU_CFLAGS"

           ;;

    x86_64)

           # ??? Only extremely old AMD cpus do not have cmpxchg16b.
@@ -1584,13 +1595,13 @@ case "$cpu" in 
           CPU_CFLAGS="-m64 -mcx16"

           LDFLAGS="-m64 $LDFLAGS"

           cross_cc_x86_64=$cc

           cross_cc_cflags_x86_64=$CPU_CFLAGS

           cross_cc_cflags_x86_64="$CPU_CFLAGS"

           ;;

    x32)

           CPU_CFLAGS="-mx32"

           LDFLAGS="-mx32 $LDFLAGS"

           cross_cc_i386=$cc

           cross_cc_cflags_i386=$CPU_CFLAGS

           cross_cc_cflags_i386="$CPU_CFLAGS"

           ;;

    # No special flags required for other host CPUs

esac
@@ -6198,7 +6209,7 @@ if { test "$cpu" = "i386" || test "$cpu" = "x86_64"; } && \ 
        fi

    done

fi

if test "$cpu" = "ppc64" && test "$targetos" != "Darwin" ; then

if test "$ARCH" = "ppc64" && test "$targetos" != "Darwin" ; then

  roms="$roms spapr-rtas"

fi
@@ -7392,7 +7403,7 @@ if test "$linux" = "yes" ; then 
  i386|x86_64|x32)

    linux_arch=x86

    ;;

  ppc|ppc64)

  ppc|ppc64|ppc64le)

    linux_arch=powerpc

    ;;

  s390x)
@@ -7553,7 +7564,8 @@ case "$target_name" in 
  ;;

  ppc)

    gdb_xml_files="power-core.xml power-fpu.xml power-altivec.xml power-spe.xml"

    target_compiler=$cross_cc_powerpc

    target_compiler=$cross_cc_ppc

    target_compiler_cflags="$cross_cc_cflags_ppc"

  ;;

  ppc64)

    TARGET_BASE_ARCH=ppc
@@ -7561,6 +7573,7 @@ case "$target_name" in 
    mttcg=yes

    gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"

    target_compiler=$cross_cc_ppc64

    target_compiler_cflags="$cross_cc_cflags_ppc64"

  ;;

  ppc64le)

    TARGET_ARCH=ppc64

docs/index.rst

+1 −0
Original line number Diff line number Diff line
@@ -12,4 +12,5 @@ Welcome to QEMU's documentation! 


   interop/index

   devel/index

   specs/index

docs/specs/index.rst

0 → 100644
+13 −0
Original line number Diff line number Diff line 
. This is the top level page for the 'specs' manual





QEMU full-system emulation guest hardware specifications

========================================================





Contents:



.. toctree::

   :maxdepth: 2



   xive

docs/specs/ppc-spapr-xive.rst

0 → 100644
+174 −0
Original line number Diff line number Diff line 
XIVE for sPAPR (pseries machines)

=================================



The POWER9 processor comes with a new interrupt controller

architecture, called XIVE as "eXternal Interrupt Virtualization

Engine". It supports a larger number of interrupt sources and offers

virtualization features which enables the HW to deliver interrupts

directly to virtual processors without hypervisor assistance.



A QEMU ``pseries`` machine (which is PAPR compliant) using POWER9

processors can run under two interrupt modes:



- *Legacy Compatibility Mode*



  the hypervisor provides identical interfaces and similar

  functionality to PAPR+ Version 2.7.  This is the default mode



  It is also referred as *XICS* in QEMU.



- *XIVE native exploitation mode*



  the hypervisor provides new interfaces to manage the XIVE control

  structures, and provides direct control for interrupt management

  through MMIO pages.



Which interrupt modes can be used by the machine is negotiated with

the guest O/S during the Client Architecture Support negotiation

sequence. The two modes are mutually exclusive.



Both interrupt mode share the same IRQ number space. See below for the

layout.



CAS Negotiation

---------------



QEMU advertises the supported interrupt modes in the device tree

property "ibm,arch-vec-5-platform-support" in byte 23 and the OS

Selection for XIVE is indicated in the "ibm,architecture-vec-5"

property byte 23.



The interrupt modes supported by the machine depend on the CPU type

(POWER9 is required for XIVE) but also on the machine property

``ic-mode`` which can be set on the command line. It can take the

following values: ``xics``, ``xive``, ``dual`` and currently ``xics``

is the default but it may change in the future.



The choosen interrupt mode is activated after a reconfiguration done

in a machine reset.



XIVE Device tree properties

---------------------------



The properties for the PAPR interrupt controller node when the *XIVE

native exploitation mode* is selected shoud contain:



- ``device_type``



  value should be "power-ivpe".



- ``compatible``



  value should be "ibm,power-ivpe".



- ``reg``



  contains the base address and size of the thread interrupt

  managnement areas (TIMA), for the User level and for the Guest OS

  level. Only the Guest OS level is taken into account today.



- ``ibm,xive-eq-sizes``



  the size of the event queues. One cell per size supported, contains

  log2 of size, in ascending order.



- ``ibm,xive-lisn-ranges``



  the IRQ interrupt number ranges assigned to the guest for the IPIs.



The root node also exports :



- ``ibm,plat-res-int-priorities``



  contains a list of priorities that the hypervisor has reserved for

  its own use.



IRQ number space

----------------



IRQ Number space of the ``pseries`` machine is 8K wide and is the same

for both interrupt mode. The different ranges are defined as follow :



- ``0x0000 .. 0x0FFF`` 4K CPU IPIs (only used under XIVE)

- ``0x1000 .. 0x1000`` 1 EPOW

- ``0x1001 .. 0x1001`` 1 HOTPLUG

- ``0x1100 .. 0x11FF`` 256 VIO devices

- ``0x1200 .. 0x127F`` 32 PHBs devices

- ``0x1280 .. 0x12FF`` unused

- ``0x1300 .. 0x1FFF`` PHB MSIs



Monitoring XIVE

---------------



The state of the XIVE interrupt controller can be queried through the

monitor commands ``info pic``. The output comes in two parts.



First, the state of the thread interrupt context registers is dumped

for each CPU :



::



   (qemu) info pic

   CPU[0000]:   QW   NSR CPPR IPB LSMFB ACK# INC AGE PIPR  W2

   CPU[0000]: USER    00   00  00    00   00  00  00   00  00000000

   CPU[0000]:   OS    00   ff  00    00   ff  00  ff   ff  80000400

   CPU[0000]: POOL    00   00  00    00   00  00  00   00  00000000

   CPU[0000]: PHYS    00   00  00    00   00  00  00   ff  00000000

   ...



In the case of a ``pseries`` machine, QEMU acts as the hypervisor and only

the O/S and USER register rings make sense. ``W2`` contains the vCPU CAM

line which is set to the VP identifier.



Then comes the routing information which aggregates the EAS and the

END configuration:



::



   ...

   LISN         PQ    EISN     CPU/PRIO EQ

   00000000 MSI --    00000010   0/6    380/16384 @1fe3e0000 ^1 [ 80000010 ... ]

   00000001 MSI --    00000010   1/6    305/16384 @1fc230000 ^1 [ 80000010 ... ]

   00000002 MSI --    00000010   2/6    220/16384 @1fc2f0000 ^1 [ 80000010 ... ]

   00000003 MSI --    00000010   3/6    201/16384 @1fc390000 ^1 [ 80000010 ... ]

   00000004 MSI -Q  M 00000000

   00000005 MSI -Q  M 00000000

   00000006 MSI -Q  M 00000000

   00000007 MSI -Q  M 00000000

   00001000 MSI --    00000012   0/6    380/16384 @1fe3e0000 ^1 [ 80000010 ... ]

   00001001 MSI --    00000013   0/6    380/16384 @1fe3e0000 ^1 [ 80000010 ... ]

   00001100 MSI --    00000100   1/6    305/16384 @1fc230000 ^1 [ 80000010 ... ]

   00001101 MSI -Q  M 00000000

   00001200 LSI -Q  M 00000000

   00001201 LSI -Q  M 00000000

   00001202 LSI -Q  M 00000000

   00001203 LSI -Q  M 00000000

   00001300 MSI --    00000102   1/6    305/16384 @1fc230000 ^1 [ 80000010 ... ]

   00001301 MSI --    00000103   2/6    220/16384 @1fc2f0000 ^1 [ 80000010 ... ]

   00001302 MSI --    00000104   3/6    201/16384 @1fc390000 ^1 [ 80000010 ... ]



The source information and configuration:



- The ``LISN`` column outputs the interrupt number of the source in

  range ``[ 0x0 ... 0x1FFF ]`` and its type : ``MSI`` or ``LSI``

- The ``PQ`` column reflects the state of the PQ bits of the source :



  - ``--`` source is ready to take events

  - ``P-`` an event was sent and an EOI is PENDING

  - ``PQ`` an event was QUEUED

  - ``-Q`` source is OFF



  a ``M`` indicates that source is *MASKED* at the EAS level,



The targeting configuration :



- The ``EISN`` column is the event data that will be queued in the event

  queue of the O/S.

- The ``CPU/PRIO`` column is the tuple defining the CPU number and

  priority queue serving the source.

- The ``EQ`` column outputs :



  - the current index of the event queue/ the max number of entries

  - the O/S event queue address

  - the toggle bit

  - the last entries that were pushed in the event queue.