Commit 5f64adc1 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191126' into staging 



target-arm queue:
 * handle FTYPE flag correctly in v7M exception return
   for v7M CPUs with an FPU (v8M CPUs were already correct)
 * versal: Add the CRP as unimplemented
 * Fix ISR_EL1 tracking when executing at EL2
 * Honor HCR_EL2.TID3 trapping requirements

# gpg: Signature made Tue 26 Nov 2019 14:11:50 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20191126:
  target/arm: Honor HCR_EL2.TID3 trapping requirements
  target/arm: Fix ISR_EL1 tracking when executing at EL2
  hw/arm: versal: Add the CRP as unimplemented
  target/arm: Fix handling of cortex-m FTYPE flag in EXCRET

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 0d4f9d7d 6a4ef4e5

hw/arm/xlnx-versal.c

+2 −0
Original line number Diff line number Diff line
@@ -257,6 +257,8 @@ static void versal_unimp(Versal *s) 
                        MM_CRL, MM_CRL_SIZE);

    versal_unimp_area(s, "crf", &s->mr_ps,

                        MM_FPD_CRF, MM_FPD_CRF_SIZE);

    versal_unimp_area(s, "crp", &s->mr_ps,

                        MM_PMC_CRP, MM_PMC_CRP_SIZE);

    versal_unimp_area(s, "iou-scntr", &s->mr_ps,

                        MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);

    versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,

include/hw/arm/xlnx-versal.h

+3 −0
Original line number Diff line number Diff line
@@ -119,4 +119,7 @@ typedef struct Versal { 
#define MM_IOU_SCNTRS_SIZE          0x10000

#define MM_FPD_CRF                  0xfd1a0000U

#define MM_FPD_CRF_SIZE             0x140000



#define MM_PMC_CRP                  0xf1260000U

#define MM_PMC_CRP_SIZE             0x10000

#endif

target/arm/helper.c

+81 −2
Original line number Diff line number Diff line
@@ -1934,8 +1934,11 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) 
    CPUState *cs = env_cpu(env);

    uint64_t hcr_el2 = arm_hcr_el2_eff(env);

    uint64_t ret = 0;

    bool allow_virt = (arm_current_el(env) == 1 &&

                       (!arm_is_secure_below_el3(env) ||

                        (env->cp15.scr_el3 & SCR_EEL2)));



    if (hcr_el2 & HCR_IMO) {

    if (allow_virt && (hcr_el2 & HCR_IMO)) {

        if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {

            ret |= CPSR_I;

        }
@@ -1945,7 +1948,7 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) 
        }

    }



    if (hcr_el2 & HCR_FMO) {

    if (allow_virt && (hcr_el2 & HCR_FMO)) {

        if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {

            ret |= CPSR_F;

        }
@@ -5975,6 +5978,26 @@ static const ARMCPRegInfo predinv_reginfo[] = { 
    REGINFO_SENTINEL

};



static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,

                                       bool isread)

{

    if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {

        return CP_ACCESS_TRAP_EL2;

    }



    return CP_ACCESS_OK;

}



static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,

                                       bool isread)

{

    if (arm_feature(env, ARM_FEATURE_V8)) {

        return access_aa64_tid3(env, ri, isread);

    }



    return CP_ACCESS_OK;

}



void register_cp_regs_for_features(ARMCPU *cpu)

{

    /* Register all the coprocessor registers based on feature bits */
@@ -5998,6 +6021,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) 
            { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->id_pfr0 },

            /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know

             * the value of the GIC field until after we define these regs.
@@ -6005,63 +6029,78 @@ void register_cp_regs_for_features(ARMCPU *cpu) 
            { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,

              .access = PL1_R, .type = ARM_CP_NO_RAW,

              .accessfn = access_aa32_tid3,

              .readfn = id_pfr1_read,

              .writefn = arm_cp_write_ignore },

            { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->id_dfr0 },

            { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->id_afr0 },

            { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->id_mmfr0 },

            { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->id_mmfr1 },

            { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->id_mmfr2 },

            { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->id_mmfr3 },

            { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->isar.id_isar0 },

            { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->isar.id_isar1 },

            { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->isar.id_isar2 },

            { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->isar.id_isar3 },

            { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->isar.id_isar4 },

            { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->isar.id_isar5 },

            { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->id_mmfr4 },

            { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa32_tid3,

              .resetvalue = cpu->isar.id_isar6 },

            REGINFO_SENTINEL

        };
@@ -6182,164 +6221,204 @@ void register_cp_regs_for_features(ARMCPU *cpu) 
            { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,

              .access = PL1_R, .type = ARM_CP_NO_RAW,

              .accessfn = access_aa64_tid3,

              .readfn = id_aa64pfr0_read,

              .writefn = arm_cp_write_ignore },

            { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = cpu->isar.id_aa64pfr1},

            { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              /* At present, only SVEver == 0 is defined anyway.  */

              .resetvalue = 0 },

            { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = cpu->id_aa64dfr0 },

            { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = cpu->id_aa64dfr1 },

            { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = cpu->id_aa64afr0 },

            { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = cpu->id_aa64afr1 },

            { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = cpu->isar.id_aa64isar0 },

            { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = cpu->isar.id_aa64isar1 },

            { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = cpu->isar.id_aa64mmfr0 },

            { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = cpu->isar.id_aa64mmfr1 },

            { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = cpu->isar.mvfr0 },

            { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = cpu->isar.mvfr1 },

            { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = cpu->isar.mvfr2 },

            { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,

              .access = PL1_R, .type = ARM_CP_CONST,

              .accessfn = access_aa64_tid3,

              .resetvalue = 0 },

            { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,

              .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,

target/arm/m_helper.c

+3 −4
Original line number Diff line number Diff line
@@ -2233,19 +2233,18 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) 
        if (env->v7m.secure) {

            lr |= R_V7M_EXCRET_S_MASK;

        }

        if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {

            lr |= R_V7M_EXCRET_FTYPE_MASK;

        }

    } else {

        lr = R_V7M_EXCRET_RES1_MASK |

            R_V7M_EXCRET_S_MASK |

            R_V7M_EXCRET_DCRS_MASK |

            R_V7M_EXCRET_FTYPE_MASK |

            R_V7M_EXCRET_ES_MASK;

        if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) {

            lr |= R_V7M_EXCRET_SPSEL_MASK;

        }

    }

    if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {

        lr |= R_V7M_EXCRET_FTYPE_MASK;

    }

    if (!arm_v7m_is_handler_mode(env)) {

        lr |= R_V7M_EXCRET_MODE_MASK;

    }