Commit 5f00335a authored by Eduardo Habkost's avatar Eduardo Habkost
Browse files

i386: Rename enum CacheType members 



Rename DCACHE to DATA_CACHE and ICACHE to INSTRUCTION_CACHE.
This avoids conflict with Linux asm/cachectl.h macros and fixes
build failure on mips hosts.

Reported-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
Message-Id: <20180717194010.30096-1-ehabkost@redhat.com>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: default avatarBabu Moger <babu.moger@amd.com>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
parent 9ba7dd14

target/i386/cpu.c

+64 −64
Original line number Diff line number Diff line
@@ -71,19 +71,19 @@ struct CPUID2CacheDescriptorInfo { 
 * From Intel SDM Volume 2A, CPUID instruction

 */

struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {

    [0x06] = { .level = 1, .type = ICACHE,        .size =   8 * KiB,

    [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size =   8 * KiB,

               .associativity = 4,  .line_size = 32, },

    [0x08] = { .level = 1, .type = ICACHE,        .size =  16 * KiB,

    [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  16 * KiB,

               .associativity = 4,  .line_size = 32, },

    [0x09] = { .level = 1, .type = ICACHE,        .size =  32 * KiB,

    [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  32 * KiB,

               .associativity = 4,  .line_size = 64, },

    [0x0A] = { .level = 1, .type = DCACHE,        .size =   8 * KiB,

    [0x0A] = { .level = 1, .type = DATA_CACHE,        .size =   8 * KiB,

               .associativity = 2,  .line_size = 32, },

    [0x0C] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,

    [0x0C] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,

               .associativity = 4,  .line_size = 32, },

    [0x0D] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,

    [0x0D] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,

               .associativity = 4,  .line_size = 64, },

    [0x0E] = { .level = 1, .type = DCACHE,        .size =  24 * KiB,

    [0x0E] = { .level = 1, .type = DATA_CACHE,        .size =  24 * KiB,

               .associativity = 6,  .line_size = 64, },

    [0x1D] = { .level = 2, .type = UNIFIED_CACHE,     .size = 128 * KiB,

               .associativity = 2,  .line_size = 64, },
@@ -97,9 +97,9 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 
    /* lines per sector is not supported cpuid2_cache_descriptor(),

    * so descriptors 0x25, 0x20 are not included

    */

    [0x2C] = { .level = 1, .type = DCACHE,        .size =  32 * KiB,

    [0x2C] = { .level = 1, .type = DATA_CACHE,        .size =  32 * KiB,

               .associativity = 8,  .line_size = 64, },

    [0x30] = { .level = 1, .type = ICACHE,        .size =  32 * KiB,

    [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  32 * KiB,

               .associativity = 8,  .line_size = 64, },

    [0x41] = { .level = 2, .type = UNIFIED_CACHE,     .size = 128 * KiB,

               .associativity = 4,  .line_size = 32, },
@@ -128,13 +128,13 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 
               .associativity = 16, .line_size = 64, },

    [0x4E] = { .level = 2, .type = UNIFIED_CACHE,     .size =   6 * MiB,

               .associativity = 24, .line_size = 64, },

    [0x60] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,

    [0x60] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,

               .associativity = 8,  .line_size = 64, },

    [0x66] = { .level = 1, .type = DCACHE,        .size =   8 * KiB,

    [0x66] = { .level = 1, .type = DATA_CACHE,        .size =   8 * KiB,

               .associativity = 4,  .line_size = 64, },

    [0x67] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,

    [0x67] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,

               .associativity = 4,  .line_size = 64, },

    [0x68] = { .level = 1, .type = DCACHE,        .size =  32 * KiB,

    [0x68] = { .level = 1, .type = DATA_CACHE,        .size =  32 * KiB,

               .associativity = 4,  .line_size = 64, },

    [0x78] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,

               .associativity = 4,  .line_size = 64, },
@@ -238,8 +238,8 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 
#define CACHE_COMPLEX_IDX     (1 << 2)



/* Encode CacheType for CPUID[4].EAX */

#define CACHE_TYPE(t) (((t) == DCACHE)  ? CACHE_TYPE_D  : \

                         ((t) == ICACHE)  ? CACHE_TYPE_I  : \

#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \

                       ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \

                       ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \

                       0 /* Invalid value */)
@@ -538,7 +538,7 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, 


/* L1 data cache: */

static CPUCacheInfo legacy_l1d_cache = {

    .type = DCACHE,

    .type = DATA_CACHE,

    .level = 1,

    .size = 32 * KiB,

    .self_init = 1,
@@ -551,7 +551,7 @@ static CPUCacheInfo legacy_l1d_cache = { 


/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */

static CPUCacheInfo legacy_l1d_cache_amd = {

    .type = DCACHE,

    .type = DATA_CACHE,

    .level = 1,

    .size = 64 * KiB,

    .self_init = 1,
@@ -565,7 +565,7 @@ static CPUCacheInfo legacy_l1d_cache_amd = { 


/* L1 instruction cache: */

static CPUCacheInfo legacy_l1i_cache = {

    .type = ICACHE,

    .type = INSTRUCTION_CACHE,

    .level = 1,

    .size = 32 * KiB,

    .self_init = 1,
@@ -578,7 +578,7 @@ static CPUCacheInfo legacy_l1i_cache = { 


/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */

static CPUCacheInfo legacy_l1i_cache_amd = {

    .type = ICACHE,

    .type = INSTRUCTION_CACHE,

    .level = 1,

    .size = 64 * KiB,

    .self_init = 1,
@@ -1310,7 +1310,7 @@ struct X86CPUDefinition { 


static CPUCaches epyc_cache_info = {

    .l1d_cache = &(CPUCacheInfo) {

        .type = DCACHE,

        .type = DATA_CACHE,

        .level = 1,

        .size = 32 * KiB,

        .line_size = 64,
@@ -1322,7 +1322,7 @@ static CPUCaches epyc_cache_info = { 
        .no_invd_sharing = true,

    },

    .l1i_cache = &(CPUCacheInfo) {

        .type = ICACHE,

        .type = INSTRUCTION_CACHE,

        .level = 1,

        .size = 64 * KiB,

        .line_size = 64,

target/i386/cpu.h

+2 −2
Original line number Diff line number Diff line
@@ -1050,8 +1050,8 @@ typedef enum TPRAccess { 
/* Cache information data structures: */



enum CacheType {

    DCACHE,

    ICACHE,

    DATA_CACHE,

    INSTRUCTION_CACHE,

    UNIFIED_CACHE

};