Commit 5efc9016 authored by Philippe Mathieu-Daudé's avatar Philippe Mathieu-Daudé Committed by Peter Maydell
Browse files

sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only 



running qtests:

  $ make check-qtest-arm
    GTESTER check-qtest-arm
  SDHC rd_4b @0x44 not implemented
  SDHC wr_4b @0x40 <- 0x89abcdef not implemented
  SDHC wr_4b @0x44 <- 0x01234567 not implemented

Signed-off-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: default avatarAlistair Francis <alistair.francis@xilinx.com>
Message-id: 20180115182436.2066-12-f4bug@amsat.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent cd209421

hw/sd/sdhci.c

+19 −4
Original line number Diff line number Diff line
@@ -899,10 +899,16 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 
        ret = s->acmd12errsts;

        break;

    case SDHC_CAPAB:

        ret = s->capareg;

        ret = (uint32_t)s->capareg;

        break;

    case SDHC_CAPAB + 4:

        ret = (uint32_t)(s->capareg >> 32);

        break;

    case SDHC_MAXCURR:

        ret = s->maxcurr;

        ret = (uint32_t)s->maxcurr;

        break;

    case SDHC_MAXCURR + 4:

        ret = (uint32_t)(s->maxcurr >> 32);

        break;

    case SDHC_ADMAERR:

        ret =  s->admaerr;
@@ -1123,6 +1129,15 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 
        }

        sdhci_update_irq(s);

        break;



    case SDHC_CAPAB:

    case SDHC_CAPAB + 4:

    case SDHC_MAXCURR:

    case SDHC_MAXCURR + 4:

        qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx

                      " <- 0x%08x read-only\n", size, offset, value >> shift);

        break;



    default:

        qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "

                      "not implemented\n", size, offset, value >> shift);
@@ -1163,8 +1178,8 @@ static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 
#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \

    /* Capabilities registers provide information on supported features

     * of this specific host controller implementation */ \

    DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \

    DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0)

    DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \

    DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0)



static void sdhci_initfn(SDHCIState *s)

{

include/hw/sd/sdhci.h

+2 −2
Original line number Diff line number Diff line
@@ -72,8 +72,8 @@ typedef struct SDHCIState { 
    uint64_t admasysaddr;  /* ADMA System Address Register */



    /* Read-only registers */

    uint32_t capareg;      /* Capabilities Register */

    uint32_t maxcurr;      /* Maximum Current Capabilities Register */

    uint64_t capareg;      /* Capabilities Register */

    uint64_t maxcurr;      /* Maximum Current Capabilities Register */



    uint8_t  *fifo_buffer; /* SD host i/o FIFO buffer */

    uint32_t buf_maxsz;