Commit 5ebafdf3 authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: Implement AArch64 SCTLR_EL1 



Implement the AArch64 view of the system control register SCTLR_EL1.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
parent b0fe2427

target-arm/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -169,7 +169,7 @@ typedef struct CPUARMState { 
    struct {

        uint32_t c0_cpuid;

        uint64_t c0_cssel; /* Cache size selection.  */

        uint32_t c1_sys; /* System control register.  */

        uint64_t c1_sys; /* System control register.  */

        uint32_t c1_coproc; /* Coprocessor access register.  */

        uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */

        uint32_t c1_scr; /* secure config register.  */

target-arm/helper.c

+2 −1
Original line number Diff line number Diff line
@@ -1948,7 +1948,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) 
    /* Generic registers whose values depend on the implementation */

    {

        ARMCPRegInfo sctlr = {

            .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,

            .name = "SCTLR", .state = ARM_CP_STATE_BOTH,

            .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,

            .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),

            .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,

            .raw_writefn = raw_write,