Commit 5de93515 authored by Bastian Koppelmann's avatar Bastian Koppelmann Committed by Peter Maydell
Browse files

target-tricore: Add instructions of SC opcode format 



Add instructions of SC opcode format.
Add helper for begin interrupt service routine.

Signed-off-by: default avatarBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-14-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent a47b50db

target-tricore/helper.h

+1 −0
Original line number Diff line number Diff line
@@ -21,3 +21,4 @@ DEF_HELPER_3(sub_ssov, i32, env, i32, i32) 
/* CSA */

DEF_HELPER_2(call, void, env, i32)

DEF_HELPER_1(ret, void, env)

DEF_HELPER_2(bisr, void, env, i32)

target-tricore/op_helper.c

+59 −0
Original line number Diff line number Diff line
@@ -122,6 +122,28 @@ static void save_context_upper(CPUTriCoreState *env, int ea, 


}



static void save_context_lower(CPUTriCoreState *env, int ea,

                               target_ulong *new_FCX)

{

    *new_FCX = cpu_ldl_data(env, ea);

    cpu_stl_data(env, ea, env->PCXI);

    cpu_stl_data(env, ea+4, env->PSW);

    cpu_stl_data(env, ea+8, env->gpr_a[2]);

    cpu_stl_data(env, ea+12, env->gpr_a[3]);

    cpu_stl_data(env, ea+16, env->gpr_d[0]);

    cpu_stl_data(env, ea+20, env->gpr_d[1]);

    cpu_stl_data(env, ea+24, env->gpr_d[2]);

    cpu_stl_data(env, ea+28, env->gpr_d[3]);

    cpu_stl_data(env, ea+32, env->gpr_a[4]);

    cpu_stl_data(env, ea+36, env->gpr_a[5]);

    cpu_stl_data(env, ea+40, env->gpr_a[6]);

    cpu_stl_data(env, ea+44, env->gpr_a[7]);

    cpu_stl_data(env, ea+48, env->gpr_d[4]);

    cpu_stl_data(env, ea+52, env->gpr_d[5]);

    cpu_stl_data(env, ea+56, env->gpr_d[6]);

    cpu_stl_data(env, ea+60, env->gpr_d[7]);

}



static void restore_context_upper(CPUTriCoreState *env, int ea,

                                  target_ulong *new_PCXI, target_ulong *new_PSW)

{
@@ -243,6 +265,43 @@ void helper_ret(CPUTriCoreState *env) 
    }

}



void helper_bisr(CPUTriCoreState *env, uint32_t const9)

{

    target_ulong tmp_FCX;

    target_ulong ea;

    target_ulong new_FCX;



    if (env->FCX == 0) {

        /* FCU trap */

    }



    tmp_FCX = env->FCX;

    ea = ((env->FCX & 0xf0000) << 12) + ((env->FCX & 0xffff) << 6);



    save_context_lower(env, ea, &new_FCX);



    /* PCXI.PCPN = ICR.CCPN */

    env->PCXI = (env->PCXI & 0xffffff) +

                 ((env->ICR & MASK_ICR_CCPN) << 24);

    /* PCXI.PIE  = ICR.IE */

    env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +

                 ((env->ICR & MASK_ICR_IE) << 15));

    /* PCXI.UL = 0 */

    env->PCXI &= ~(MASK_PCXI_UL);

    /* PCXI[19: 0] = FCX[19: 0] */

    env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);

    /* FXC[19: 0] = new_FCX[19: 0] */

    env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);

    /* ICR.IE = 1 */

    env->ICR |= MASK_ICR_IE;



    env->ICR |= const9; /* ICR.CCPN = const9[7: 0];*/



    if (tmp_FCX == env->LCX) {

        /* FCD trap */

    }

}



static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env,

                                                        uint32_t exception,

                                                        int error_code,

target-tricore/translate.c

+48 −0
Original line number Diff line number Diff line
@@ -680,6 +680,42 @@ static void decode_ssr_opc(DisasContext *ctx, int op1) 
    }

}



static void decode_sc_opc(DisasContext *ctx, int op1)

{

    int32_t const16;



    const16 = MASK_OP_SC_CONST8(ctx->opcode);



    switch (op1) {

    case OPC1_16_SC_AND:

        tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);

        break;

    case OPC1_16_SC_BISR:

        gen_helper_1arg(bisr, const16 & 0xff);

        break;

    case OPC1_16_SC_LD_A:

        gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);

        break;

    case OPC1_16_SC_LD_W:

        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);

        break;

    case OPC1_16_SC_MOV:

        tcg_gen_movi_tl(cpu_gpr_d[15], const16);

        break;

    case OPC1_16_SC_OR:

        tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);

        break;

    case OPC1_16_SC_ST_A:

        gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);

        break;

    case OPC1_16_SC_ST_W:

        gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);

        break;

    case OPC1_16_SC_SUB_A:

        tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);

        break;

    }

}

static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)

{

    int op1;
@@ -816,6 +852,18 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) 
        address = MASK_OP_SBR_DISP4(ctx->opcode);

        gen_compute_branch(ctx, op1, r1, 0, 0, address);

        break;

/* SC-format */

    case OPC1_16_SC_AND:

    case OPC1_16_SC_BISR:

    case OPC1_16_SC_LD_A:

    case OPC1_16_SC_LD_W:

    case OPC1_16_SC_MOV:

    case OPC1_16_SC_OR:

    case OPC1_16_SC_ST_A:

    case OPC1_16_SC_ST_W:

    case OPC1_16_SC_SUB_A:

        decode_sc_opc(ctx, op1);

        break;

    }

}