Commit 5dd13f2a authored by Cathy Zhang's avatar Cathy Zhang Committed by Paolo Bonzini
Browse files

target/i386: Add SERIALIZE cpu feature 

The availability of the SERIALIZATION instruction is indicated
by the presence of the CPUID feature flag SERIALIZE, which is
defined as CPUID.(EAX=7,ECX=0):ECX[bit 14].

The release spec link is as follows:
https://software.intel.com/content/dam/develop/public/us/en/documents/\
architecture-instruction-set-extensions-programming-reference.pdf

The associated kvm patch link is as follows:
https://lore.kernel.org/patchwork/patch/1268025/



Signed-off-by: default avatarCathy Zhang <cathy.zhang@intel.com>
Message-Id: <1593991036-12183-2-git-send-email-cathy.zhang@intel.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 2f7057ac

target/i386/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -986,7 +986,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
            NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",

            NULL, NULL, NULL, NULL,

            "avx512-vp2intersect", NULL, "md-clear", NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, "serialize", NULL,

            NULL, NULL, NULL /* pconfig */, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, "spec-ctrl", "stibp",

target/i386/cpu.h

+2 −0
Original line number Diff line number Diff line
@@ -777,6 +777,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 
#define CPUID_7_0_EDX_AVX512_4FMAPS     (1U << 3)

/* AVX512 Vector Pair Intersection to a Pair of Mask Registers */

#define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)

/* SERIALIZE instruction */

#define CPUID_7_0_EDX_SERIALIZE         (1U << 14)

/* Speculation Control */

#define CPUID_7_0_EDX_SPEC_CTRL         (1U << 26)

/* Single Thread Indirect Branch Predictors */