Commit 5d05b9d4 authored by Aaron Lindsay's avatar Aaron Lindsay Committed by Peter Maydell
Browse files

target/arm: Reorganize PMCCNTR accesses 



pmccntr_read and pmccntr_write contained duplicate code that was already
being handled by pmccntr_sync. Consolidate the duplicated code into two
functions: pmccntr_op_start and pmccntr_op_finish. Add a companion to
c15_ccnt in CPUARMState so that we can simultaneously save both the
architectural register value and the last underlying cycle count - this
ensures time isn't lost and will also allow us to access the 'old'
architectural register value in order to detect overflows in later
patches.

Signed-off-by: default avatarAaron Lindsay <alindsay@codeaurora.org>
Signed-off-by: default avatarAaron Lindsay <aclindsa@gmail.com>
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Message-id: 20181211151945.29137-3-aaron@os.amperecomputing.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 8c07559f

target/arm/cpu.h

+29 −8
Original line number Diff line number Diff line
@@ -473,10 +473,20 @@ typedef struct CPUARMState { 
        uint64_t oslsr_el1; /* OS Lock Status */

        uint64_t mdcr_el2;

        uint64_t mdcr_el3;

        /* If the counter is enabled, this stores the last time the counter

         * was reset. Otherwise it stores the counter value

        /* Stores the architectural value of the counter *the last time it was

         * updated* by pmccntr_op_start. Accesses should always be surrounded

         * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest

         * architecturally-correct value is being read/set.

         */

        uint64_t c15_ccnt;

        /* Stores the delta between the architectural value and the underlying

         * cycle count during normal operation. It is used to update c15_ccnt

         * to be the correct architectural value before accesses. During

         * accesses, c15_ccnt_delta contains the underlying count being used

         * for the access, after which it reverts to the delta value in

         * pmccntr_op_finish.

         */

        uint64_t c15_ccnt_delta;

        uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */

        uint64_t vpidr_el2; /* Virtualization Processor ID Register */

        uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
@@ -971,15 +981,26 @@ int cpu_arm_signal_handler(int host_signum, void *pinfo, 
                           void *puc);



/**

 * pmccntr_sync

 * pmccntr_op_start/finish

 * @env: CPUARMState

 *

 * Synchronises the counter in the PMCCNTR. This must always be called twice,

 * once before any action that might affect the timer and again afterwards.

 * The function is used to swap the state of the register if required.

 * This only happens when not in user mode (!CONFIG_USER_ONLY)

 * Convert the counter in the PMCCNTR between its delta form (the typical mode

 * when it's enabled) and the guest-visible value. These two calls must always

 * surround any action which might affect the counter.

 */

void pmccntr_sync(CPUARMState *env);

void pmccntr_op_start(CPUARMState *env);

void pmccntr_op_finish(CPUARMState *env);



/**

 * pmu_op_start/finish

 * @env: CPUARMState

 *

 * Convert all PMU counters between their delta form (the typical mode when

 * they are enabled) and the guest-visible values. These two calls must

 * surround any action which might affect the counters.

 */

void pmu_op_start(CPUARMState *env);

void pmu_op_finish(CPUARMState *env);



/* SCTLR bit meanings. Several bits have been reused in newer

 * versions of the architecture; in that case we define constants

target/arm/helper.c

+69 −45
Original line number Diff line number Diff line
@@ -1085,28 +1085,63 @@ static inline bool arm_ccnt_enabled(CPUARMState *env) 


    return true;

}



void pmccntr_sync(CPUARMState *env)

/*

 * Ensure c15_ccnt is the guest-visible count so that operations such as

 * enabling/disabling the counter or filtering, modifying the count itself,

 * etc. can be done logically. This is essentially a no-op if the counter is

 * not enabled at the time of the call.

 */

void pmccntr_op_start(CPUARMState *env)

{

    uint64_t temp_ticks;



    temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),

    uint64_t cycles = 0;

    cycles = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),

                          ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);



    if (arm_ccnt_enabled(env)) {

        uint64_t eff_cycles = cycles;

        if (env->cp15.c9_pmcr & PMCRD) {

            /* Increment once every 64 processor clock cycles */

        temp_ticks /= 64;

            eff_cycles /= 64;

        }



        env->cp15.c15_ccnt = eff_cycles - env->cp15.c15_ccnt_delta;

    }

    env->cp15.c15_ccnt_delta = cycles;

}



/*

 * If PMCCNTR is enabled, recalculate the delta between the clock and the

 * guest-visible count. A call to pmccntr_op_finish should follow every call to

 * pmccntr_op_start.

 */

void pmccntr_op_finish(CPUARMState *env)

{

    if (arm_ccnt_enabled(env)) {

        env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;

        uint64_t prev_cycles = env->cp15.c15_ccnt_delta;



        if (env->cp15.c9_pmcr & PMCRD) {

            /* Increment once every 64 processor clock cycles */

            prev_cycles /= 64;

        }



        env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt;

    }

}



void pmu_op_start(CPUARMState *env)

{

    pmccntr_op_start(env);

}



void pmu_op_finish(CPUARMState *env)

{

    pmccntr_op_finish(env);

}



static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,

                       uint64_t value)

{

    pmccntr_sync(env);

    pmu_op_start(env);



    if (value & PMCRC) {

        /* The counter has been reset */
@@ -1117,26 +1152,16 @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 
    env->cp15.c9_pmcr &= ~0x39;

    env->cp15.c9_pmcr |= (value & 0x39);



    pmccntr_sync(env);

    pmu_op_finish(env);

}



static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)

{

    uint64_t total_ticks;



    if (!arm_ccnt_enabled(env)) {

        /* Counter is disabled, do not change value */

        return env->cp15.c15_ccnt;

    }



    total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),

                           ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);



    if (env->cp15.c9_pmcr & PMCRD) {

        /* Increment once every 64 processor clock cycles */

        total_ticks /= 64;

    }

    return total_ticks - env->cp15.c15_ccnt;

    uint64_t ret;

    pmccntr_op_start(env);

    ret = env->cp15.c15_ccnt;

    pmccntr_op_finish(env);

    return ret;

}



static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -1153,22 +1178,9 @@ static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, 
static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,

                        uint64_t value)

{

    uint64_t total_ticks;



    if (!arm_ccnt_enabled(env)) {

        /* Counter is disabled, set the absolute value */

    pmccntr_op_start(env);

    env->cp15.c15_ccnt = value;

        return;

    }



    total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),

                           ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);



    if (env->cp15.c9_pmcr & PMCRD) {

        /* Increment once every 64 processor clock cycles */

        total_ticks /= 64;

    }

    env->cp15.c15_ccnt = total_ticks - value;

    pmccntr_op_finish(env);

}



static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -1181,7 +1193,19 @@ static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, 


#else /* CONFIG_USER_ONLY */



void pmccntr_sync(CPUARMState *env)

void pmccntr_op_start(CPUARMState *env)

{

}



void pmccntr_op_finish(CPUARMState *env)

{

}



void pmu_op_start(CPUARMState *env)

{

}



void pmu_op_finish(CPUARMState *env)

{

}
@@ -1190,9 +1214,9 @@ void pmccntr_sync(CPUARMState *env) 
static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,

                            uint64_t value)

{

    pmccntr_sync(env);

    pmccntr_op_start(env);

    env->cp15.pmccfiltr_el0 = value & 0xfc000000;

    pmccntr_sync(env);

    pmccntr_op_finish(env);

}



static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,