Commit 5cb287d2 authored by Chenyi Qiang's avatar Chenyi Qiang Committed by Eduardo Habkost
Browse files

target/i386: add fast short REP MOV support 



For CPUs support fast short REP MOV[CPUID.(EAX=7,ECX=0):EDX(bit4)], e.g
Icelake and Tigerlake, expose it to the guest VM.

Reviewed-by: default avatarEduardo Habkost <ehabkost@redhat.com>
Signed-off-by: default avatarChenyi Qiang <chenyi.qiang@intel.com>
Message-Id: <20200714084148.26690-2-chenyi.qiang@intel.com>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
parent f9f08e7c

target/i386/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -984,7 +984,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
        .type = CPUID_FEATURE_WORD,

        .feat_names = {

            NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",

            NULL, NULL, NULL, NULL,

            "fsrm", NULL, NULL, NULL,

            "avx512-vp2intersect", NULL, "md-clear", NULL,

            NULL, NULL, "serialize", NULL,

            "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,

target/i386/cpu.h

+2 −0
Original line number Diff line number Diff line
@@ -775,6 +775,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 
#define CPUID_7_0_EDX_AVX512_4VNNIW     (1U << 2)

/* AVX512 Multiply Accumulation Single Precision */

#define CPUID_7_0_EDX_AVX512_4FMAPS     (1U << 3)

/* Fast Short Rep Mov */

#define CPUID_7_0_EDX_FSRM              (1U << 4)

/* AVX512 Vector Pair Intersection to a Pair of Mask Registers */

#define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)

/* SERIALIZE instruction */