Commit 5cad8ca5 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging 



x86 queue, 2018-01-17

Highlight: new CPU models that expose CPU features that guests
can use to mitigate CVE-2017-5715 (Spectre variant #2).

# gpg: Signature made Thu 18 Jan 2018 02:00:03 GMT
# gpg:                using RSA key 0x2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-pull-request:
  i386: Add EPYC-IBPB CPU model
  i386: Add new -IBRS versions of Intel CPU models
  i386: Add FEAT_8000_0008_EBX CPUID feature word
  i386: Add spec-ctrl CPUID bit
  i386: Add support for SPEC_CTRL MSR
  i386: Change X86CPUDefinition::model_id to const char*
  target/i386: add clflushopt to "Skylake-Server" cpu model
  pc: add 2.12 machine types

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 6e03cc5c 6cfbc54e

hw/i386/pc_piix.c

+12 −3
Original line number Diff line number Diff line
@@ -426,21 +426,30 @@ static void pc_i440fx_machine_options(MachineClass *m) 
    m->default_display = "std";

}



static void pc_i440fx_2_11_machine_options(MachineClass *m)

static void pc_i440fx_2_12_machine_options(MachineClass *m)

{

    pc_i440fx_machine_options(m);

    m->alias = "pc";

    m->is_default = 1;

}



DEFINE_I440FX_MACHINE(v2_12, "pc-i440fx-2.12", NULL,

                      pc_i440fx_2_12_machine_options);



static void pc_i440fx_2_11_machine_options(MachineClass *m)

{

    pc_i440fx_2_12_machine_options(m);

    m->is_default = 0;

    m->alias = NULL;

    SET_MACHINE_COMPAT(m, PC_COMPAT_2_11);

}



DEFINE_I440FX_MACHINE(v2_11, "pc-i440fx-2.11", NULL,

                      pc_i440fx_2_11_machine_options);



static void pc_i440fx_2_10_machine_options(MachineClass *m)

{

    pc_i440fx_2_11_machine_options(m);

    m->is_default = 0;

    m->alias = NULL;

    SET_MACHINE_COMPAT(m, PC_COMPAT_2_10);

    m->auto_enable_numa_with_memhp = false;

}

hw/i386/pc_q35.c

+11 −2
Original line number Diff line number Diff line
@@ -303,19 +303,28 @@ static void pc_q35_machine_options(MachineClass *m) 
    m->max_cpus = 288;

}



static void pc_q35_2_11_machine_options(MachineClass *m)

static void pc_q35_2_12_machine_options(MachineClass *m)

{

    pc_q35_machine_options(m);

    m->alias = "q35";

}



DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,

                   pc_q35_2_12_machine_options);



static void pc_q35_2_11_machine_options(MachineClass *m)

{

    pc_q35_2_12_machine_options(m);

    m->alias = NULL;

    SET_MACHINE_COMPAT(m, PC_COMPAT_2_11);

}



DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,

                   pc_q35_2_11_machine_options);



static void pc_q35_2_10_machine_options(MachineClass *m)

{

    pc_q35_2_11_machine_options(m);

    m->alias = NULL;

    SET_MACHINE_COMPAT(m, PC_COMPAT_2_10);

    m->numa_auto_assign_ram = numa_legacy_auto_assign_ram;

    m->auto_enable_numa_with_memhp = false;

include/hw/i386/pc.h

+8 −0
Original line number Diff line number Diff line
@@ -321,6 +321,14 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t); 
int e820_get_num_entries(void);

bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);



#define PC_COMPAT_2_11 \

    HW_COMPAT_2_11 \

    {\

        .driver   = "Skylake-Server" "-" TYPE_X86_CPU,\

        .property = "clflushopt",\

        .value    = "off",\

    },



#define PC_COMPAT_2_10 \

    HW_COMPAT_2_10 \

    {\

target/i386/cpu.c

+452 −5

File changed.

Preview size limit exceeded, changes collapsed.

target/i386/cpu.h

+7 −0
Original line number Diff line number Diff line
@@ -353,6 +353,7 @@ typedef enum X86Seg { 
#define MSR_IA32_APICBASE_BASE          (0xfffffU<<12)

#define MSR_IA32_FEATURE_CONTROL        0x0000003a

#define MSR_TSC_ADJUST                  0x0000003b

#define MSR_IA32_SPEC_CTRL              0x48

#define MSR_IA32_TSCDEADLINE            0x6e0



#define FEATURE_CONTROL_LOCKED                    (1<<0)
@@ -471,6 +472,7 @@ typedef enum FeatureWord { 
    FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */

    FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */

    FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */

    FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */

    FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */

    FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */

    FEAT_HYPERV_EAX,    /* CPUID[4000_0003].EAX */
@@ -666,6 +668,9 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 


#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */

#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */

#define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */



#define CPUID_8000_0008_EBX_IBPB    (1U << 12) /* Indirect Branch Prediction Barrier */



#define CPUID_XSAVE_XSAVEOPT   (1U << 0)

#define CPUID_XSAVE_XSAVEC     (1U << 1)
@@ -1125,6 +1130,8 @@ typedef struct CPUX86State { 


    uint32_t pkru;



    uint64_t spec_ctrl;



    /* End of state preserved by INIT (dummy marker).  */

    struct {} end_init_save;