Commit 5c36d895 authored by Alex Bennée's avatar Alex Bennée Committed by Peter Maydell
Browse files

arm/translate-a64: add all FP16 ops in simd_scalar_pairwise 



I only needed to do a little light re-factoring to support the
half-precision helpers.

Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-30-alex.bennee@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 70b4e6a4

target/arm/translate-a64.c

+54 −26
Original line number Diff line number Diff line
@@ -6418,22 +6418,28 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) 
    case 0x2f: /* FMINP */

        /* FP op, size[0] is 32 or 64 bit*/

        if (!u) {

            if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

                unallocated_encoding(s);

                return;

            } else {

                size = MO_16;

            }

        } else {

            size = extract32(size, 0, 1) ? MO_64 : MO_32;

        }



        if (!fp_access_check(s)) {

            return;

        }



        size = extract32(size, 0, 1) ? 3 : 2;

        fpst = get_fpstatus_ptr(false);

        fpst = get_fpstatus_ptr(size == MO_16);

        break;

    default:

        unallocated_encoding(s);

        return;

    }



    if (size == 3) {

    if (size == MO_64) {

        TCGv_i64 tcg_op1 = tcg_temp_new_i64();

        TCGv_i64 tcg_op2 = tcg_temp_new_i64();

        TCGv_i64 tcg_res = tcg_temp_new_i64();
@@ -6474,9 +6480,30 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) 
        TCGv_i32 tcg_op2 = tcg_temp_new_i32();

        TCGv_i32 tcg_res = tcg_temp_new_i32();



        read_vec_element_i32(s, tcg_op1, rn, 0, MO_32);

        read_vec_element_i32(s, tcg_op2, rn, 1, MO_32);

        read_vec_element_i32(s, tcg_op1, rn, 0, size);

        read_vec_element_i32(s, tcg_op2, rn, 1, size);



        if (size == MO_16) {

            switch (opcode) {

            case 0xc: /* FMAXNMP */

                gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);

                break;

            case 0xd: /* FADDP */

                gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);

                break;

            case 0xf: /* FMAXP */

                gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);

                break;

            case 0x2c: /* FMINNMP */

                gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);

                break;

            case 0x2f: /* FMINP */

                gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);

                break;

            default:

                g_assert_not_reached();

            }

        } else {

            switch (opcode) {

            case 0xc: /* FMAXNMP */

                gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
@@ -6496,6 +6523,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) 
            default:

                g_assert_not_reached();

            }

        }



        write_fp_sreg(s, rd, tcg_res);