Commit 5be5e8ed authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Add ZCR_ELx 



Define ZCR_EL[1-3].

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Message-id: 20180123035349.24538-5-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent ef401601

target/arm/cpu.h

+5 −0
Original line number Diff line number Diff line
@@ -549,6 +549,9 @@ typedef struct CPUARMState { 
         */

        float_status fp_status;

        float_status standard_fp_status;



        /* ZCR_EL[1-3] */

        uint64_t zcr_el[4];

    } vfp;

    uint64_t exclusive_addr;

    uint64_t exclusive_val;
@@ -923,6 +926,8 @@ void pmccntr_sync(CPUARMState *env); 
#define CPTR_TCPAC    (1U << 31)

#define CPTR_TTA      (1U << 20)

#define CPTR_TFP      (1U << 10)

#define CPTR_TZ       (1U << 8)   /* CPTR_EL2 */

#define CPTR_EZ       (1U << 8)   /* CPTR_EL3 */



#define MDCR_EPMAD    (1U << 21)

#define MDCR_EDAD     (1U << 20)

target/arm/helper.c

+131 −0
Original line number Diff line number Diff line
@@ -4266,6 +4266,125 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { 
    REGINFO_SENTINEL

};



/* Return the exception level to which SVE-disabled exceptions should

 * be taken, or 0 if SVE is enabled.

 */

static int sve_exception_el(CPUARMState *env)

{

#ifndef CONFIG_USER_ONLY

    unsigned current_el = arm_current_el(env);



    /* The CPACR.ZEN controls traps to EL1:

     * 0, 2 : trap EL0 and EL1 accesses

     * 1    : trap only EL0 accesses

     * 3    : trap no accesses

     */

    switch (extract32(env->cp15.cpacr_el1, 16, 2)) {

    default:

        if (current_el <= 1) {

            /* Trap to PL1, which might be EL1 or EL3 */

            if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {

                return 3;

            }

            return 1;

        }

        break;

    case 1:

        if (current_el == 0) {

            return 1;

        }

        break;

    case 3:

        break;

    }



    /* Similarly for CPACR.FPEN, after having checked ZEN.  */

    switch (extract32(env->cp15.cpacr_el1, 20, 2)) {

    default:

        if (current_el <= 1) {

            if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {

                return 3;

            }

            return 1;

        }

        break;

    case 1:

        if (current_el == 0) {

            return 1;

        }

        break;

    case 3:

        break;

    }



    /* CPTR_EL2.  Check both TZ and TFP.  */

    if (current_el <= 2

        && (env->cp15.cptr_el[2] & (CPTR_TFP | CPTR_TZ))

        && !arm_is_secure_below_el3(env)) {

        return 2;

    }



    /* CPTR_EL3.  Check both EZ and TFP.  */

    if (!(env->cp15.cptr_el[3] & CPTR_EZ)

        || (env->cp15.cptr_el[3] & CPTR_TFP)) {

        return 3;

    }

#endif

    return 0;

}



static CPAccessResult zcr_access(CPUARMState *env, const ARMCPRegInfo *ri,

                                 bool isread)

{

    switch (sve_exception_el(env)) {

    case 3:

        return CP_ACCESS_TRAP_EL3;

    case 2:

        return CP_ACCESS_TRAP_EL2;

    case 1:

        return CP_ACCESS_TRAP;

    }

    return CP_ACCESS_OK;

}



static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,

                      uint64_t value)

{

    /* Bits other than [3:0] are RAZ/WI.  */

    raw_write(env, ri, value & 0xf);

}



static const ARMCPRegInfo zcr_el1_reginfo = {

    .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,

    .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,

    .access = PL1_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,

    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),

    .writefn = zcr_write, .raw_writefn = raw_write

};



static const ARMCPRegInfo zcr_el2_reginfo = {

    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,

    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,

    .access = PL2_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,

    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),

    .writefn = zcr_write, .raw_writefn = raw_write

};



static const ARMCPRegInfo zcr_no_el2_reginfo = {

    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,

    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,

    .access = PL2_RW, .type = ARM_CP_64BIT,

    .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore

};



static const ARMCPRegInfo zcr_el3_reginfo = {

    .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,

    .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,

    .access = PL3_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,

    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),

    .writefn = zcr_write, .raw_writefn = raw_write

};



void hw_watchpoint_update(ARMCPU *cpu, int n)

{

    CPUARMState *env = &cpu->env;
@@ -5332,6 +5451,18 @@ void register_cp_regs_for_features(ARMCPU *cpu) 
        }

        define_one_arm_cp_reg(cpu, &sctlr);

    }



    if (arm_feature(env, ARM_FEATURE_SVE)) {

        define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);

        if (arm_feature(env, ARM_FEATURE_EL2)) {

            define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);

        } else {

            define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);

        }

        if (arm_feature(env, ARM_FEATURE_EL3)) {

            define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);

        }

    }

}



void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)