Commit 5a922419 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200605' into staging 



target-arm queue:
 hw/ssi/imx_spi: Handle tx burst lengths other than 8 correctly
 hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
 hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
 target/arm: Convert crypto insns to gvec
 hw/adc/stm32f2xx_adc: Correct memory region size and access size
 tests/acceptance: Add a boot test for the xlnx-versal-virt machine
 docs/system: Document Aspeed boards
 raspi: Add model of the USB controller
 target/arm: Convert 2-reg-and-shift and 1-reg-imm Neon insns to decodetree

# gpg: Signature made Fri 05 Jun 2020 17:48:39 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200605: (29 commits)
  target/arm: Convert Neon one-register-and-immediate insns to decodetree
  target/arm: Convert VCVT fixed-point ops to decodetree
  target/arm: Convert Neon VSHLL, VMOVL to decodetree
  target/arm: Convert Neon narrowing shifts with op==9 to decodetree
  target/arm: Convert Neon narrowing shifts with op==8 to decodetree
  target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree
  target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree
  target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree
  target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree
  raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host
  wire in the dwc-hsotg (dwc2) USB host controller emulation
  usb: add short-packet handling to usb-storage driver
  dwc-hsotg (dwc2) USB host controller emulation
  dwc-hsotg (dwc2) USB host controller state definitions
  dwc-hsotg (dwc2) USB host controller register definitions
  raspi: add BCM2835 SOC MPHI emulation
  docs/system: Document Aspeed boards
  tests/acceptance: Add a boot test for the xlnx-versal-virt machine
  hw/adc/stm32f2xx_adc: Correct memory region size and access size
  target/arm: Split helper_crypto_sm3tt
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 175198ad 2c35a39e

docs/system/arm/aspeed.rst

0 → 100644
+85 −0
Original line number Diff line number Diff line 
Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``)

==================================================================



The QEMU Aspeed machines model BMCs of various OpenPOWER systems and

Aspeed evaluation boards. They are based on different releases of the

Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the

AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600

with dual cores ARM Cortex A7 CPUs (1.2GHz).



The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C,

etc.



AST2400 SoC based machines :



- ``palmetto-bmc``         OpenPOWER Palmetto POWER8 BMC



AST2500 SoC based machines :



- ``ast2500-evb``          Aspeed AST2500 Evaluation board

- ``romulus-bmc``          OpenPOWER Romulus POWER9 BMC

- ``witherspoon-bmc``      OpenPOWER Witherspoon POWER9 BMC

- ``sonorapass-bmc``       OCP SonoraPass BMC

- ``swift-bmc``            OpenPOWER Swift BMC POWER9



AST2600 SoC based machines :



- ``ast2600-evb``          Aspeed AST2600 Evaluation board (Cortex A7)

- ``tacoma-bmc``           OpenPOWER Witherspoon POWER9 AST2600 BMC



Supported devices

-----------------



 * SMP (for the AST2600 Cortex-A7)

 * Interrupt Controller (VIC)

 * Timer Controller

 * RTC Controller

 * I2C Controller

 * System Control Unit (SCU)

 * SRAM mapping

 * X-DMA Controller (basic interface)

 * Static Memory Controller (SMC or FMC) - Only SPI Flash support

 * SPI Memory Controller

 * USB 2.0 Controller

 * SD/MMC storage controllers

 * SDRAM controller (dummy interface for basic settings and training)

 * Watchdog Controller

 * GPIO Controller (Master only)

 * UART

 * Ethernet controllers





Missing devices

---------------



 * Coprocessor support

 * ADC (out of tree implementation)

 * PWM and Fan Controller

 * LPC Bus Controller

 * Slave GPIO Controller

 * Super I/O Controller

 * Hash/Crypto Engine

 * PCI-Express 1 Controller

 * Graphic Display Controller

 * PECI Controller

 * MCTP Controller

 * Mailbox Controller

 * Virtual UART

 * eSPI Controller

 * I3C Controller



Boot options

------------



The Aspeed machines can be started using the -kernel option to load a

Linux kernel or from a firmare image which can be downloaded from the

OpenPOWER jenkins :



   https://openpower.xyz/



The image should be attached as an MTD drive. Run :



.. code-block:: bash



  $ qemu-system-arm -M romulus-bmc -nic user \

	-drive file=flash-romulus,format=raw,if=mtd -nographic

docs/system/target-arm.rst

+1 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ undocumented; you can get a complete list by running 
   arm/realview

   arm/versatile

   arm/vexpress

   arm/aspeed

   arm/musicpal

   arm/nseries

   arm/orangepi

hw/adc/stm32f2xx_adc.c

+3 −1
Original line number Diff line number Diff line
@@ -246,6 +246,8 @@ static const MemoryRegionOps stm32f2xx_adc_ops = { 
    .read = stm32f2xx_adc_read,

    .write = stm32f2xx_adc_write,

    .endianness = DEVICE_NATIVE_ENDIAN,

    .impl.min_access_size = 4,

    .impl.max_access_size = 4,

};



static const VMStateDescription vmstate_stm32f2xx_adc = {
@@ -278,7 +280,7 @@ static void stm32f2xx_adc_init(Object *obj) 
    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);



    memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,

                          TYPE_STM32F2XX_ADC, 0xFF);

                          TYPE_STM32F2XX_ADC, 0x100);

    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);

}

hw/arm/bcm2835_peripherals.c

+37 −1
Original line number Diff line number Diff line
@@ -125,6 +125,17 @@ static void bcm2835_peripherals_init(Object *obj) 
                                   OBJECT(&s->sdhci.sdbus));

    object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",

                                   OBJECT(&s->sdhost.sdbus));



    /* Mphi */

    sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi),

                          TYPE_BCM2835_MPHI);



    /* DWC2 */

    sysbus_init_child_obj(obj, "dwc2", &s->dwc2, sizeof(s->dwc2),

                          TYPE_DWC2_USB);



    object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",

                                   OBJECT(&s->gpu_bus_mr));

}



static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
@@ -360,6 +371,32 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) 


    object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus");



    /* Mphi */

    object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }



    memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET,

                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0));

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0,

        qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,

                               INTERRUPT_HOSTPORT));



    /* DWC2 */

    object_property_set_bool(OBJECT(&s->dwc2), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }



    memory_region_add_subregion(&s->peri_mr, USB_OTG_OFFSET,

                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dwc2), 0));

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->dwc2), 0,

        qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,

                               INTERRUPT_USB));



    create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);

    create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);

    create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
@@ -373,7 +410,6 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) 
    create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80);

    create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000);

    create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000);

    create_unimp(s, &s->dwc2, "dwc-usb2", USB_OTG_OFFSET, 0x1000);

    create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100);

}

hw/arm/pxa2xx.c

+49 −17
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include "sysemu/blockdev.h"

#include "sysemu/qtest.h"

#include "qemu/cutils.h"

#include "qemu/log.h"



static struct {

    hwaddr io_base;
@@ -112,7 +113,9 @@ static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, 
        return s->pm_regs[addr >> 2];

    default:

    fail:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

        break;

    }

    return 0;
@@ -143,8 +146,9 @@ static void pxa2xx_pm_write(void *opaque, hwaddr addr, 
            s->pm_regs[addr >> 2] = value;

            break;

        }



        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

        break;

    }

}
@@ -185,7 +189,9 @@ static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, 
        return s->cm_regs[CCCR >> 2] | (3 << 28);



    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

        break;

    }

    return 0;
@@ -210,7 +216,9 @@ static void pxa2xx_cm_write(void *opaque, hwaddr addr, 
        break;



    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

        break;

    }

}
@@ -415,7 +423,9 @@ static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, 
            return s->mm_regs[addr >> 2];

        /* fall through */

    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

        break;

    }

    return 0;
@@ -434,7 +444,9 @@ static void pxa2xx_mm_write(void *opaque, hwaddr addr, 
        }



    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

        break;

    }

}
@@ -641,7 +653,9 @@ static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, 
    case SSACD:

        return s->ssacd;

    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

        break;

    }

    return 0;
@@ -733,7 +747,9 @@ static void pxa2xx_ssp_write(void *opaque, hwaddr addr, 
        break;



    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

        break;

    }

}
@@ -995,7 +1011,9 @@ static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 
        else

            return s->last_swcr;

    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

        break;

    }

    return 0;
@@ -1101,7 +1119,9 @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 
        break;



    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

    }

}
@@ -1354,7 +1374,9 @@ static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, 
            s->ibmr = 0;

        return s->ibmr;

    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

        break;

    }

    return 0;
@@ -1427,7 +1449,9 @@ static void pxa2xx_i2c_write(void *opaque, hwaddr addr, 
        break;



    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

    }

}
@@ -1628,7 +1652,9 @@ static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, 
        }

        return 0;

    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

        break;

    }

    return 0;
@@ -1685,7 +1711,9 @@ static void pxa2xx_i2s_write(void *opaque, hwaddr addr, 
        }

        break;

    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

    }

}
@@ -1870,7 +1898,9 @@ static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, 
    case ICFOR:

        return s->rx_len;

    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

        break;

    }

    return 0;
@@ -1922,7 +1952,9 @@ static void pxa2xx_fir_write(void *opaque, hwaddr addr, 
    case ICFOR:

        break;

    default:

        printf("%s: Bad register " REG_FMT "\n", __func__, addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

                      __func__, addr);

    }

}