Commit 59afd43d authored by Max Filippov's avatar Max Filippov
Browse files

target/xtensa: work around missing SR definitions 



Xtensa configuration overlays for recent releases may have special
registers for which [rwx]sr opcodes are defined, but they are not listed
as SR in xtensa_sysreg_name and associated functions. As a result
generic translate_[rwx]sr* functions generate access to uninitialized
cpu_SR causing segfault at runtime.
Don't try to access cpu_SR for such registers, ignore writes and return
0 for reads.

Cc: qemu-stable@nongnu.org
Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
parent 648db196

target/xtensa/translate.c

+34 −14
Original line number Diff line number Diff line
@@ -2191,7 +2191,11 @@ static void translate_rsil(DisasContext *dc, const OpcodeArg arg[], 
static void translate_rsr(DisasContext *dc, const OpcodeArg arg[],

                          const uint32_t par[])

{

    if (sr_name[par[0]]) {

        tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);

    } else {

        tcg_gen_movi_i32(arg[0].out, 0);

    }

}



static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[],
@@ -2563,14 +2567,18 @@ static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[], 
static void translate_wsr(DisasContext *dc, const OpcodeArg arg[],

                          const uint32_t par[])

{

    if (sr_name[par[0]]) {

        tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);

    }

}



static void translate_wsr_mask(DisasContext *dc, const OpcodeArg arg[],

                               const uint32_t par[])

{

    if (sr_name[par[0]]) {

        tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]);

    }

}



static void translate_wsr_acchi(DisasContext *dc, const OpcodeArg arg[],

                                const uint32_t par[])
@@ -2775,23 +2783,31 @@ static void translate_xor(DisasContext *dc, const OpcodeArg arg[], 
static void translate_xsr(DisasContext *dc, const OpcodeArg arg[],

                          const uint32_t par[])

{

    if (sr_name[par[0]]) {

        TCGv_i32 tmp = tcg_temp_new_i32();



        tcg_gen_mov_i32(tmp, arg[0].in);

        tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);

        tcg_gen_mov_i32(cpu_SR[par[0]], tmp);

        tcg_temp_free(tmp);

    } else {

        tcg_gen_movi_i32(arg[0].out, 0);

    }

}



static void translate_xsr_mask(DisasContext *dc, const OpcodeArg arg[],

                               const uint32_t par[])

{

    if (sr_name[par[0]]) {

        TCGv_i32 tmp = tcg_temp_new_i32();



        tcg_gen_mov_i32(tmp, arg[0].in);

        tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);

        tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);

        tcg_temp_free(tmp);

    } else {

        tcg_gen_movi_i32(arg[0].out, 0);

    }

}



static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[],
@@ -2819,7 +2835,11 @@ static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[], 
{ \

    TCGv_i32 tmp = tcg_temp_new_i32(); \

 \

    if (sr_name[par[0]]) { \

        tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \

    } else { \

        tcg_gen_movi_i32(tmp, 0); \

    } \

    translate_wsr_##name(dc, arg, par); \

    tcg_gen_mov_i32(arg[0].out, tmp); \

    tcg_temp_free(tmp); \