Commit 597360c0 authored by Xiaoyao Li's avatar Xiaoyao Li Committed by Paolo Bonzini
Browse files

target/i386: define a new MSR based feature word - FEAT_CORE_CAPABILITY 

MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, which only
enumerates the feature split lock detection (via bit 5) by now.

The existence of MSR IA32_CORE_CAPABILITY is enumerated by CPUID.7_0:EDX[30].

The latest kernel patches about them can be found here:
https://lkml.org/lkml/2019/4/24/1909



Signed-off-by: default avatarXiaoyao Li <xiaoyao.li@linux.intel.com>
Message-Id: <20190617153654.916-1-xiaoyao.li@linux.intel.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 128531d9

target/i386/cpu.c

+21 −1
Original line number Diff line number Diff line
@@ -1085,7 +1085,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, "spec-ctrl", "stibp",

            NULL, "arch-capabilities", NULL, "ssbd",

            NULL, "arch-capabilities", "core-capability", "ssbd",

        },

        .cpuid = {

            .eax = 7,
@@ -1203,6 +1203,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
            }

        },

    },

    [FEAT_CORE_CAPABILITY] = {

        .type = MSR_FEATURE_WORD,

        .feat_names = {

            NULL, NULL, NULL, NULL,

            NULL, "split-lock-detect", NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

        },

        .msr = {

            .index = MSR_IA32_CORE_CAPABILITY,

            .cpuid_dep = {

                FEAT_7_0_EDX,

                CPUID_7_0_EDX_CORE_CAPABILITY,

            },

        },

    },

};



typedef struct X86RegisterInfo32 {

target/i386/cpu.h

+5 −0
Original line number Diff line number Diff line
@@ -345,6 +345,7 @@ typedef enum X86Seg { 
#define MSR_IA32_SPEC_CTRL              0x48

#define MSR_VIRT_SSBD                   0xc001011f

#define MSR_IA32_PRED_CMD               0x49

#define MSR_IA32_CORE_CAPABILITY        0xcf

#define MSR_IA32_ARCH_CAPABILITIES      0x10a

#define MSR_IA32_TSCDEADLINE            0x6e0
@@ -496,6 +497,7 @@ typedef enum FeatureWord { 
    FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */

    FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */

    FEAT_ARCH_CAPABILITIES,

    FEAT_CORE_CAPABILITY,

    FEATURE_WORDS,

} FeatureWord;
@@ -687,6 +689,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */

#define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */

#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)  /*Arch Capabilities*/

#define CPUID_7_0_EDX_CORE_CAPABILITY   (1U << 30)  /*Core Capability*/

#define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */



#define CPUID_8000_0008_EBX_WBNOINVD  (1U << 9)  /* Write back and
@@ -734,6 +737,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 
#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)

#define MSR_ARCH_CAP_SSB_NO     (1U << 4)



#define MSR_CORE_CAP_SPLIT_LOCK_DETECT  (1U << 5)



/* Supported Hyper-V Enlightenments */

#define HYPERV_FEAT_RELAXED             0

#define HYPERV_FEAT_VAPIC               1

target/i386/kvm.c

+9 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ static bool has_msr_spec_ctrl; 
static bool has_msr_virt_ssbd;

static bool has_msr_smi_count;

static bool has_msr_arch_capabs;

static bool has_msr_core_capabs;



static uint32_t has_architectural_pmu_version;

static uint32_t num_architectural_pmu_gp_counters;
@@ -1842,6 +1843,9 @@ static int kvm_get_supported_msrs(KVMState *s) 
                case MSR_IA32_ARCH_CAPABILITIES:

                    has_msr_arch_capabs = true;

                    break;

                case MSR_IA32_CORE_CAPABILITY:

                    has_msr_core_capabs = true;

                    break;

                }

            }

        }
@@ -2368,6 +2372,11 @@ static int kvm_put_msrs(X86CPU *cpu, int level) 
                          env->features[FEAT_ARCH_CAPABILITIES]);

    }



    if (has_msr_core_capabs) {

        kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,

                          env->features[FEAT_CORE_CAPABILITY]);

    }



    /*

     * The following MSRs have side effects on the guest or are too heavy

     * for normal writeback. Limit them to reset or full state updates.