Commit 59093cc4 authored by Alistair Francis's avatar Alistair Francis
Browse files

hw/char: Convert the Ibex UART to use the registerfields API 



Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Message-id: 06372c9cdeec715077899e71c858d9f0a2a3395b.1594332223.git.alistair.francis@wdc.com
Message-Id: <06372c9cdeec715077899e71c858d9f0a2a3395b.1594332223.git.alistair.francis@wdc.com>
parent 940aabb9

hw/char/ibex_uart.c

+65 −65
Original line number Diff line number Diff line
@@ -36,25 +36,25 @@ 


static void ibex_uart_update_irqs(IbexUartState *s)

{

    if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_WATERMARK) {

    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) {

        qemu_set_irq(s->tx_watermark, 1);

    } else {

        qemu_set_irq(s->tx_watermark, 0);

    }



    if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_WATERMARK) {

    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_WATERMARK_MASK) {

        qemu_set_irq(s->rx_watermark, 1);

    } else {

        qemu_set_irq(s->rx_watermark, 0);

    }



    if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_EMPTY) {

    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_EMPTY_MASK) {

        qemu_set_irq(s->tx_empty, 1);

    } else {

        qemu_set_irq(s->tx_empty, 0);

    }



    if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_OVERFLOW) {

    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_OVERFLOW_MASK) {

        qemu_set_irq(s->rx_overflow, 1);

    } else {

        qemu_set_irq(s->rx_overflow, 0);
@@ -65,7 +65,7 @@ static int ibex_uart_can_receive(void *opaque) 
{

    IbexUartState *s = opaque;



    if (s->uart_ctrl & UART_CTRL_RX_ENABLE) {

    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {

        return 1;

    }
@@ -75,16 +75,16 @@ static int ibex_uart_can_receive(void *opaque) 
static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)

{

    IbexUartState *s = opaque;

    uint8_t rx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_RXILVL)

                            >> FIFO_CTRL_RXILVL_SHIFT;

    uint8_t rx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_RXILVL_MASK)

                            >> R_FIFO_CTRL_RXILVL_SHIFT;



    s->uart_rdata = *buf;



    s->uart_status &= ~UART_STATUS_RXIDLE;

    s->uart_status &= ~UART_STATUS_RXEMPTY;

    s->uart_status &= ~R_STATUS_RXIDLE_MASK;

    s->uart_status &= ~R_STATUS_RXEMPTY_MASK;



    if (size > rx_fifo_level) {

        s->uart_intr_state |= INTR_STATE_RX_WATERMARK;

        s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;

    }



    ibex_uart_update_irqs(s);
@@ -94,8 +94,8 @@ static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond, 
                               void *opaque)

{

    IbexUartState *s = opaque;

    uint8_t tx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL)

                            >> FIFO_CTRL_TXILVL_SHIFT;

    uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)

                            >> R_FIFO_CTRL_TXILVL_SHIFT;

    int ret;



    /* instant drain the fifo when there's no back-end */
@@ -105,10 +105,10 @@ static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond, 
    }



    if (!s->tx_level) {

        s->uart_status &= ~UART_STATUS_TXFULL;

        s->uart_status |= UART_STATUS_TXEMPTY;

        s->uart_intr_state |= INTR_STATE_TX_EMPTY;

        s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;

        s->uart_status &= ~R_STATUS_TXFULL_MASK;

        s->uart_status |= R_STATUS_TXEMPTY_MASK;

        s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;

        s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;

        ibex_uart_update_irqs(s);

        return FALSE;

    }
@@ -131,18 +131,18 @@ static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond, 


    /* Clear the TX Full bit */

    if (s->tx_level != IBEX_UART_TX_FIFO_SIZE) {

        s->uart_status &= ~UART_STATUS_TXFULL;

        s->uart_status &= ~R_STATUS_TXFULL_MASK;

    }



    /* Disable the TX_WATERMARK IRQ */

    if (s->tx_level < tx_fifo_level) {

        s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;

        s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;

    }



    /* Set TX empty */

    if (s->tx_level == 0) {

        s->uart_status |= UART_STATUS_TXEMPTY;

        s->uart_intr_state |= INTR_STATE_TX_EMPTY;

        s->uart_status |= R_STATUS_TXEMPTY_MASK;

        s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;

    }



    ibex_uart_update_irqs(s);
@@ -153,8 +153,8 @@ static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf, 
                               int size)

{

    uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

    uint8_t tx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL)

                            >> FIFO_CTRL_TXILVL_SHIFT;

    uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)

                            >> R_FIFO_CTRL_TXILVL_SHIFT;



    if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) {

        size = IBEX_UART_TX_FIFO_SIZE - s->tx_level;
@@ -165,16 +165,16 @@ static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf, 
    s->tx_level += size;



    if (s->tx_level > 0) {

        s->uart_status &= ~UART_STATUS_TXEMPTY;

        s->uart_status &= ~R_STATUS_TXEMPTY_MASK;

    }



    if (s->tx_level >= tx_fifo_level) {

        s->uart_intr_state |= INTR_STATE_TX_WATERMARK;

        s->uart_intr_state |= R_INTR_STATE_TX_WATERMARK_MASK;

        ibex_uart_update_irqs(s);

    }



    if (s->tx_level == IBEX_UART_TX_FIFO_SIZE) {

        s->uart_status |= UART_STATUS_TXFULL;

        s->uart_status |= R_STATUS_TXFULL_MASK;

    }



    timer_mod(s->fifo_trigger_handle, current_time +
@@ -208,7 +208,7 @@ static uint64_t ibex_uart_get_baud(IbexUartState *s) 
{

    uint64_t baud;



    baud = ((s->uart_ctrl & UART_CTRL_NCO) >> 16);

    baud = ((s->uart_ctrl & R_CTRL_NCO_MASK) >> 16);

    baud *= clock_get_hz(s->f_clk);

    baud >>= 20;
@@ -221,43 +221,43 @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr, 
    IbexUartState *s = opaque;

    uint64_t retvalue = 0;



    switch (addr) {

    case IBEX_UART_INTR_STATE:

    switch (addr >> 2) {

    case R_INTR_STATE:

        retvalue = s->uart_intr_state;

        break;

    case IBEX_UART_INTR_ENABLE:

    case R_INTR_ENABLE:

        retvalue = s->uart_intr_enable;

        break;

    case IBEX_UART_INTR_TEST:

    case R_INTR_TEST:

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: wdata is write only\n", __func__);

        break;



    case IBEX_UART_CTRL:

    case R_CTRL:

        retvalue = s->uart_ctrl;

        break;

    case IBEX_UART_STATUS:

    case R_STATUS:

        retvalue = s->uart_status;

        break;



    case IBEX_UART_RDATA:

    case R_RDATA:

        retvalue = s->uart_rdata;

        if (s->uart_ctrl & UART_CTRL_RX_ENABLE) {

        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {

            qemu_chr_fe_accept_input(&s->chr);



            s->uart_status |= UART_STATUS_RXIDLE;

            s->uart_status |= UART_STATUS_RXEMPTY;

            s->uart_status |= R_STATUS_RXIDLE_MASK;

            s->uart_status |= R_STATUS_RXEMPTY_MASK;

        }

        break;

    case IBEX_UART_WDATA:

    case R_WDATA:

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: wdata is write only\n", __func__);

        break;



    case IBEX_UART_FIFO_CTRL:

    case R_FIFO_CTRL:

        retvalue = s->uart_fifo_ctrl;

        break;

    case IBEX_UART_FIFO_STATUS:

    case R_FIFO_STATUS:

        retvalue = s->uart_fifo_status;



        retvalue |= s->tx_level & 0x1F;
@@ -266,17 +266,17 @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr, 
                      "%s: RX fifos are not supported\n", __func__);

        break;



    case IBEX_UART_OVRD:

    case R_OVRD:

        retvalue = s->uart_ovrd;

        qemu_log_mask(LOG_UNIMP,

                      "%s: ovrd is not supported\n", __func__);

        break;

    case IBEX_UART_VAL:

    case R_VAL:

        retvalue = s->uart_val;

        qemu_log_mask(LOG_UNIMP,

                      "%s: val is not supported\n", __func__);

        break;

    case IBEX_UART_TIMEOUT_CTRL:

    case R_TIMEOUT_CTRL:

        retvalue = s->uart_timeout_ctrl;

        qemu_log_mask(LOG_UNIMP,

                      "%s: timeout_ctrl is not supported\n", __func__);
@@ -296,95 +296,95 @@ static void ibex_uart_write(void *opaque, hwaddr addr, 
    IbexUartState *s = opaque;

    uint32_t value = val64;



    switch (addr) {

    case IBEX_UART_INTR_STATE:

    switch (addr >> 2) {

    case R_INTR_STATE:

        /* Write 1 clear */

        s->uart_intr_state &= ~value;

        ibex_uart_update_irqs(s);

        break;

    case IBEX_UART_INTR_ENABLE:

    case R_INTR_ENABLE:

        s->uart_intr_enable = value;

        ibex_uart_update_irqs(s);

        break;

    case IBEX_UART_INTR_TEST:

    case R_INTR_TEST:

        s->uart_intr_state |= value;

        ibex_uart_update_irqs(s);

        break;



    case IBEX_UART_CTRL:

    case R_CTRL:

        s->uart_ctrl = value;



        if (value & UART_CTRL_NF) {

        if (value & R_CTRL_NF_MASK) {

            qemu_log_mask(LOG_UNIMP,

                          "%s: UART_CTRL_NF is not supported\n", __func__);

        }

        if (value & UART_CTRL_SLPBK) {

        if (value & R_CTRL_SLPBK_MASK) {

            qemu_log_mask(LOG_UNIMP,

                          "%s: UART_CTRL_SLPBK is not supported\n", __func__);

        }

        if (value & UART_CTRL_LLPBK) {

        if (value & R_CTRL_LLPBK_MASK) {

            qemu_log_mask(LOG_UNIMP,

                          "%s: UART_CTRL_LLPBK is not supported\n", __func__);

        }

        if (value & UART_CTRL_PARITY_EN) {

        if (value & R_CTRL_PARITY_EN_MASK) {

            qemu_log_mask(LOG_UNIMP,

                          "%s: UART_CTRL_PARITY_EN is not supported\n",

                          __func__);

        }

        if (value & UART_CTRL_PARITY_ODD) {

        if (value & R_CTRL_PARITY_ODD_MASK) {

            qemu_log_mask(LOG_UNIMP,

                          "%s: UART_CTRL_PARITY_ODD is not supported\n",

                          __func__);

        }

        if (value & UART_CTRL_RXBLVL) {

        if (value & R_CTRL_RXBLVL_MASK) {

            qemu_log_mask(LOG_UNIMP,

                          "%s: UART_CTRL_RXBLVL is not supported\n", __func__);

        }

        if (value & UART_CTRL_NCO) {

        if (value & R_CTRL_NCO_MASK) {

            uint64_t baud = ibex_uart_get_baud(s);



            s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;

        }

        break;

    case IBEX_UART_STATUS:

    case R_STATUS:

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: status is read only\n", __func__);

        break;



    case IBEX_UART_RDATA:

    case R_RDATA:

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: rdata is read only\n", __func__);

        break;

    case IBEX_UART_WDATA:

    case R_WDATA:

        uart_write_tx_fifo(s, (uint8_t *) &value, 1);

        break;



    case IBEX_UART_FIFO_CTRL:

    case R_FIFO_CTRL:

        s->uart_fifo_ctrl = value;



        if (value & FIFO_CTRL_RXRST) {

        if (value & R_FIFO_CTRL_RXRST_MASK) {

            qemu_log_mask(LOG_UNIMP,

                          "%s: RX fifos are not supported\n", __func__);

        }

        if (value & FIFO_CTRL_TXRST) {

        if (value & R_FIFO_CTRL_TXRST_MASK) {

            s->tx_level = 0;

        }

        break;

    case IBEX_UART_FIFO_STATUS:

    case R_FIFO_STATUS:

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: fifo_status is read only\n", __func__);

        break;



    case IBEX_UART_OVRD:

    case R_OVRD:

        s->uart_ovrd = value;

        qemu_log_mask(LOG_UNIMP,

                      "%s: ovrd is not supported\n", __func__);

        break;

    case IBEX_UART_VAL:

    case R_VAL:

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: val is read only\n", __func__);

        break;

    case IBEX_UART_TIMEOUT_CTRL:

    case R_TIMEOUT_CTRL:

        s->uart_timeout_ctrl = value;

        qemu_log_mask(LOG_UNIMP,

                      "%s: timeout_ctrl is not supported\n", __func__);
@@ -409,7 +409,7 @@ static void fifo_trigger_update(void *opaque) 
{

    IbexUartState *s = opaque;



    if (s->uart_ctrl & UART_CTRL_TX_ENABLE) {

    if (s->uart_ctrl & R_CTRL_TX_ENABLE_MASK) {

        ibex_uart_xmit(NULL, G_IO_OUT, s);

    }

}

include/hw/char/ibex_uart.h

+35 −41
Original line number Diff line number Diff line
@@ -26,50 +26,44 @@ 
#define HW_IBEX_UART_H



#include "hw/sysbus.h"

#include "hw/registerfields.h"

#include "chardev/char-fe.h"

#include "qemu/timer.h"



#define IBEX_UART_INTR_STATE   0x00

    #define INTR_STATE_TX_WATERMARK (1 << 0)

    #define INTR_STATE_RX_WATERMARK (1 << 1)

    #define INTR_STATE_TX_EMPTY     (1 << 2)

    #define INTR_STATE_RX_OVERFLOW  (1 << 3)

#define IBEX_UART_INTR_ENABLE  0x04

#define IBEX_UART_INTR_TEST    0x08



#define IBEX_UART_CTRL         0x0c

    #define UART_CTRL_TX_ENABLE     (1 << 0)

    #define UART_CTRL_RX_ENABLE     (1 << 1)

    #define UART_CTRL_NF            (1 << 2)

    #define UART_CTRL_SLPBK         (1 << 4)

    #define UART_CTRL_LLPBK         (1 << 5)

    #define UART_CTRL_PARITY_EN     (1 << 6)

    #define UART_CTRL_PARITY_ODD    (1 << 7)

    #define UART_CTRL_RXBLVL        (3 << 8)

    #define UART_CTRL_NCO           (0xFFFF << 16)



#define IBEX_UART_STATUS       0x10

    #define UART_STATUS_TXFULL  (1 << 0)

    #define UART_STATUS_RXFULL  (1 << 1)

    #define UART_STATUS_TXEMPTY (1 << 2)

    #define UART_STATUS_RXIDLE  (1 << 4)

    #define UART_STATUS_RXEMPTY (1 << 5)



#define IBEX_UART_RDATA        0x14

#define IBEX_UART_WDATA        0x18



#define IBEX_UART_FIFO_CTRL    0x1c

    #define FIFO_CTRL_RXRST          (1 << 0)

    #define FIFO_CTRL_TXRST          (1 << 1)

    #define FIFO_CTRL_RXILVL         (7 << 2)

    #define FIFO_CTRL_RXILVL_SHIFT   (2)

    #define FIFO_CTRL_TXILVL         (3 << 5)

    #define FIFO_CTRL_TXILVL_SHIFT   (5)



#define IBEX_UART_FIFO_STATUS  0x20

#define IBEX_UART_OVRD         0x24

#define IBEX_UART_VAL          0x28

#define IBEX_UART_TIMEOUT_CTRL 0x2c

REG32(INTR_STATE, 0x00)

    FIELD(INTR_STATE, TX_WATERMARK, 0, 1)

    FIELD(INTR_STATE, RX_WATERMARK, 1, 1)

    FIELD(INTR_STATE, TX_EMPTY, 2, 1)

    FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)

REG32(INTR_ENABLE, 0x04)

REG32(INTR_TEST, 0x08)

REG32(CTRL, 0x0C)

    FIELD(CTRL, TX_ENABLE, 0, 1)

    FIELD(CTRL, RX_ENABLE, 1, 1)

    FIELD(CTRL, NF, 2, 1)

    FIELD(CTRL, SLPBK, 4, 1)

    FIELD(CTRL, LLPBK, 5, 1)

    FIELD(CTRL, PARITY_EN, 6, 1)

    FIELD(CTRL, PARITY_ODD, 7, 1)

    FIELD(CTRL, RXBLVL, 8, 2)

    FIELD(CTRL, NCO, 16, 16)

REG32(STATUS, 0x10)

    FIELD(STATUS, TXFULL, 0, 1)

    FIELD(STATUS, RXFULL, 1, 1)

    FIELD(STATUS, TXEMPTY, 2, 1)

    FIELD(STATUS, RXIDLE, 4, 1)

    FIELD(STATUS, RXEMPTY, 5, 1)

REG32(RDATA, 0x14)

REG32(WDATA, 0x18)

REG32(FIFO_CTRL, 0x1c)

    FIELD(FIFO_CTRL, RXRST, 0, 1)

    FIELD(FIFO_CTRL, TXRST, 1, 1)

    FIELD(FIFO_CTRL, RXILVL, 2, 3)

    FIELD(FIFO_CTRL, TXILVL, 5, 2)

REG32(FIFO_STATUS, 0x20)

REG32(OVRD, 0x24)

REG32(VAL, 0x28)

REG32(TIMEOUT_CTRL, 0x2c)



#define IBEX_UART_TX_FIFO_SIZE 16

#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */