Commit 58d2a9ae authored by Aurelien Jarno's avatar Aurelien Jarno
Browse files

target/sh4: optimize gen_store_fpr64 



Using extr and avoiding intermediate temps.

Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
parent b3995c23

target/sh4/translate.c

+1 −7
Original line number Diff line number Diff line
@@ -305,13 +305,7 @@ static inline void gen_load_fpr64(TCGv_i64 t, int reg) 


static inline void gen_store_fpr64 (TCGv_i64 t, int reg)

{

    TCGv_i32 tmp = tcg_temp_new_i32();

    tcg_gen_extrl_i64_i32(tmp, t);

    tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);

    tcg_gen_shri_i64(t, t, 32);

    tcg_gen_extrl_i64_i32(tmp, t);

    tcg_gen_mov_i32(cpu_fregs[reg], tmp);

    tcg_temp_free_i32(tmp);

    tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t);

}



#define B3_0 (ctx->opcode & 0xf)