Commit 57dfc2c4 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190704-1' into staging 



target-arm queue:
 * more code-movement to separate TCG-only functions into their own files
 * Correct VMOV_imm_dp handling of short vectors
 * Execute Thumb instructions when their condbits are 0xf
 * armv7m_systick: Forbid non-privileged accesses
 * Use _ra versions of cpu_stl_data() in v7M helpers
 * v8M: Check state of exception being returned from
 * v8M: Forcibly clear negative-priority exceptions on deactivate

# gpg: Signature made Thu 04 Jul 2019 17:31:22 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190704-1:
  target/arm: Correct VMOV_imm_dp handling of short vectors
  target/arm: Execute Thumb instructions when their condbits are 0xf
  hw/timer/armv7m_systick: Forbid non-privileged accesses
  target/arm: Use _ra versions of cpu_stl_data() in v7M helpers
  target/arm: v8M: Check state of exception being returned from
  arm v8M: Forcibly clear negative-priority exceptions on deactivate
  target/arm/helper: Move M profile routines to m_helper.c
  target/arm: Restrict semi-hosting to TCG
  target/arm: Move debug routines to debug_helper.c

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents c3e1d838 89a11ff7

hw/intc/armv7m_nvic.c

+48 −6
Original line number Diff line number Diff line
@@ -812,16 +812,46 @@ void armv7m_nvic_get_pending_irq_info(void *opaque, 
int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)

{

    NVICState *s = (NVICState *)opaque;

    VecInfo *vec;

    VecInfo *vec = NULL;

    int ret;



    assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);



    /*

     * For negative priorities, v8M will forcibly deactivate the appropriate

     * NMI or HardFault regardless of what interrupt we're being asked to

     * deactivate (compare the DeActivate() pseudocode). This is a guard

     * against software returning from NMI or HardFault with a corrupted

     * IPSR and leaving the CPU in a negative-priority state.

     * v7M does not do this, but simply deactivates the requested interrupt.

     */

    if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {

        switch (armv7m_nvic_raw_execution_priority(s)) {

        case -1:

            if (s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {

                vec = &s->vectors[ARMV7M_EXCP_HARD];

            } else {

                vec = &s->sec_vectors[ARMV7M_EXCP_HARD];

            }

            break;

        case -2:

            vec = &s->vectors[ARMV7M_EXCP_NMI];

            break;

        case -3:

            vec = &s->sec_vectors[ARMV7M_EXCP_HARD];

            break;

        default:

            break;

        }

    }



    if (!vec) {

        if (secure && exc_is_banked(irq)) {

            vec = &s->sec_vectors[irq];

        } else {

            vec = &s->vectors[irq];

        }

    }



    trace_nvic_complete_irq(irq, secure);
@@ -830,7 +860,19 @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) 
        return -1;

    }



    /*

     * If this is a configurable exception and it is currently

     * targeting the opposite security state from the one we're trying

     * to complete it for, this counts as an illegal exception return.

     * We still need to deactivate whatever vector the logic above has

     * selected, though, as it might not be the same as the one for the

     * requested exception number.

     */

    if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) {

        ret = -1;

    } else {

        ret = nvic_rettobase(s);

    }



    vec->active = 0;

    if (vec->level) {

hw/timer/armv7m_systick.c

+20 −6
Original line number Diff line number Diff line
@@ -75,11 +75,17 @@ static void systick_timer_tick(void *opaque) 
    }

}



static uint64_t systick_read(void *opaque, hwaddr addr, unsigned size)

static MemTxResult systick_read(void *opaque, hwaddr addr, uint64_t *data,

                                unsigned size, MemTxAttrs attrs)

{

    SysTickState *s = opaque;

    uint32_t val;



    if (attrs.user) {

        /* Generate BusFault for unprivileged accesses */

        return MEMTX_ERROR;

    }



    switch (addr) {

    case 0x0: /* SysTick Control and Status.  */

        val = s->control;
@@ -121,14 +127,21 @@ static uint64_t systick_read(void *opaque, hwaddr addr, unsigned size) 
    }



    trace_systick_read(addr, val, size);

    return val;

    *data = val;

    return MEMTX_OK;

}



static void systick_write(void *opaque, hwaddr addr,

                          uint64_t value, unsigned size)

static MemTxResult systick_write(void *opaque, hwaddr addr,

                                 uint64_t value, unsigned size,

                                 MemTxAttrs attrs)

{

    SysTickState *s = opaque;



    if (attrs.user) {

        /* Generate BusFault for unprivileged accesses */

        return MEMTX_ERROR;

    }



    trace_systick_write(addr, value, size);



    switch (addr) {
@@ -172,11 +185,12 @@ static void systick_write(void *opaque, hwaddr addr, 
        qemu_log_mask(LOG_GUEST_ERROR,

                      "SysTick: Bad write offset 0x%" HWADDR_PRIx "\n", addr);

    }

    return MEMTX_OK;

}



static const MemoryRegionOps systick_ops = {

    .read = systick_read,

    .write = systick_write,

    .read_with_attrs = systick_read,

    .write_with_attrs = systick_write,

    .endianness = DEVICE_NATIVE_ENDIAN,

    .valid.min_access_size = 4,

    .valid.max_access_size = 4,

target/arm/Makefile.objs

+3 −2
Original line number Diff line number Diff line 
obj-y += arm-semi.o

obj-$(CONFIG_TCG) += arm-semi.o

obj-y += helper.o vfp_helper.o

obj-y += cpu.o gdbstub.o

obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
@@ -32,10 +32,11 @@ target/arm/translate-sve.o: target/arm/decode-sve.inc.c 
target/arm/translate.o: target/arm/decode-vfp.inc.c

target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c



obj-y += tlb_helper.o

obj-y += tlb_helper.o debug_helper.o

obj-y += translate.o op_helper.o

obj-y += crypto_helper.o

obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o

obj-y += m_helper.o



obj-$(CONFIG_SOFTMMU) += psci.o

target/arm/cpu.c

+3 −6
Original line number Diff line number Diff line
@@ -2578,19 +2578,16 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) 
    cc->gdb_arch_name = arm_gdb_arch_name;

    cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;

    cc->gdb_stop_before_watchpoint = true;

    cc->debug_excp_handler = arm_debug_excp_handler;

    cc->debug_check_watchpoint = arm_debug_check_watchpoint;

#if !defined(CONFIG_USER_ONLY)

    cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;

#endif



    cc->disas_set_info = arm_disas_set_info;

#ifdef CONFIG_TCG

    cc->tcg_initialize = arm_translate_init;

    cc->tlb_fill = arm_cpu_tlb_fill;

    cc->debug_excp_handler = arm_debug_excp_handler;

    cc->debug_check_watchpoint = arm_debug_check_watchpoint;

#if !defined(CONFIG_USER_ONLY)

    cc->do_unaligned_access = arm_cpu_do_unaligned_access;

    cc->do_transaction_failed = arm_cpu_do_transaction_failed;

    cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;

#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */

#endif

}

target/arm/cpu.h

+7 −0
Original line number Diff line number Diff line
@@ -964,7 +964,14 @@ static inline void aarch64_sve_change_el(CPUARMState *env, int o, 
{ }

#endif



#if !defined(CONFIG_TCG)

static inline target_ulong do_arm_semihosting(CPUARMState *env)

{

    g_assert_not_reached();

}

#else

target_ulong do_arm_semihosting(CPUARMState *env);

#endif

void aarch64_sync_32_to_64(CPUARMState *env);

void aarch64_sync_64_to_32(CPUARMState *env);