Loading hw/mips/mips_int.c +3 −8 Original line number Diff line number Diff line Loading @@ -47,18 +47,13 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) if (level) { env->CP0_Cause |= 1 << (irq + CP0Ca_IP); if (kvm_enabled() && irq == 2) { kvm_mips_set_interrupt(cpu, irq, level); } } else { env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); } if (kvm_enabled() && irq == 2) { kvm_mips_set_interrupt(cpu, irq, level); } } if (env->CP0_Cause & CP0Ca_IP_mask) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); Loading Loading
hw/mips/mips_int.c +3 −8 Original line number Diff line number Diff line Loading @@ -47,18 +47,13 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) if (level) { env->CP0_Cause |= 1 << (irq + CP0Ca_IP); if (kvm_enabled() && irq == 2) { kvm_mips_set_interrupt(cpu, irq, level); } } else { env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); } if (kvm_enabled() && irq == 2) { kvm_mips_set_interrupt(cpu, irq, level); } } if (env->CP0_Cause & CP0Ca_IP_mask) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); Loading