Commit 55ed8d60 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20171113' into staging 



target-arm queue:
 * translate-a64.c: silence gcc5 warning
 * highbank: validate register offset before access
 * MAINTAINERS: Add entries for Smartfusion2
 * accel/tcg/translate-all: expand cpu_restore_state addr check
   (so usermode insn aborts don't crash with an assertion failure)
 * fix TCG initialization of some Arm boards by allowing them
   to specify min/default number of CPUs to create

# gpg: Signature made Mon 13 Nov 2017 14:11:09 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20171113:
  accel/tcg/translate-all: expand cpu_restore_state addr check
  hw: add .min_cpus and .default_cpus fields to machine_class
  xlnx-zcu102: Specify the max number of CPUs for the EP108
  xlnx-zcu102: Add an info message deprecating the EP108
  xlnx-zynqmp: Properly support the smp command line option
  qom: move CPUClass.tcg_initialize to a global
  MAINTAINERS: Add entries for Smartfusion2
  highbank: validate register offset before access
  arm/translate-a64: mark path as unreachable to eliminate warning

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 2e550e31 d25f2a72

MAINTAINERS

+17 −0
Original line number Diff line number Diff line
@@ -564,6 +564,23 @@ M: Alistair Francis <alistair@alistair23.me> 
S: Maintained

F: hw/arm/netduino2.c



SmartFusion2

M: Subbaraya Sundeep <sundeep.lkml@gmail.com>

S: Maintained

F: hw/arm/msf2-soc.c

F: hw/misc/msf2-sysreg.c

F: hw/timer/mss-timer.c

F: hw/ssi/mss-spi.c

F: include/hw/arm/msf2-soc.h

F: include/hw/misc/msf2-sysreg.h

F: include/hw/timer/mss-timer.h

F: include/hw/ssi/mss-spi.h



Emcraft M2S-FG484

M: Subbaraya Sundeep <sundeep.lkml@gmail.com>

S: Maintained

F: hw/arm/msf2-som.c



CRIS Machines

-------------

Axis Dev88

accel/tcg/translate-all.c

+29 −23
Original line number Diff line number Diff line
@@ -352,28 +352,33 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, 
    return 0;

}



bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)

bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc)

{

    TranslationBlock *tb;

    bool r = false;

    uintptr_t check_offset;



    /* A retaddr of zero is invalid so we really shouldn't have ended

     * up here. The target code has likely forgotten to check retaddr

     * != 0 before attempting to restore state. We return early to

     * avoid blowing up on a recursive tb_lock(). The target must have

     * previously survived a failed cpu_restore_state because

     * tb_find_pc(0) would have failed anyway. It still should be

     * fixed though.

    /* The host_pc has to be in the region of current code buffer. If

     * it is not we will not be able to resolve it here. The two cases

     * where host_pc will not be correct are:

     *

     *  - fault during translation (instruction fetch)

     *  - fault from helper (not using GETPC() macro)

     *

     * Either way we need return early to avoid blowing up on a

     * recursive tb_lock() as we can't resolve it here.

     *

     * We are using unsigned arithmetic so if host_pc <

     * tcg_init_ctx.code_gen_buffer check_offset will wrap to way

     * above the code_gen_buffer_size

     */

    check_offset = host_pc - (uintptr_t) tcg_init_ctx.code_gen_buffer;



    if (!retaddr) {

        return r;

    }



    if (check_offset < tcg_init_ctx.code_gen_buffer_size) {

        tb_lock();

    tb = tb_find_pc(retaddr);

        tb = tb_find_pc(host_pc);

        if (tb) {

        cpu_restore_state_from_tb(cpu, tb, retaddr);

            cpu_restore_state_from_tb(cpu, tb, host_pc);

            if (tb->cflags & CF_NOCACHE) {

                /* one-shot translation, invalidate it immediately */

                tb_phys_invalidate(tb, -1);
@@ -382,6 +387,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) 
            r = true;

        }

        tb_unlock();

    }



    return r;

}

exec.c

+3 −2
Original line number Diff line number Diff line
@@ -792,11 +792,12 @@ void cpu_exec_initfn(CPUState *cpu) 
void cpu_exec_realizefn(CPUState *cpu, Error **errp)

{

    CPUClass *cc = CPU_GET_CLASS(cpu);

    static bool tcg_target_initialized;



    cpu_list_add(cpu);



    if (tcg_enabled() && !cc->tcg_initialized) {

        cc->tcg_initialized = true;

    if (tcg_enabled() && !tcg_target_initialized) {

        tcg_target_initialized = true;

        cc->tcg_initialize();

    }

hw/arm/exynos4_boards.c

+4 −8
Original line number Diff line number Diff line
@@ -27,7 +27,6 @@ 
#include "qemu-common.h"

#include "cpu.h"

#include "sysemu/sysemu.h"

#include "sysemu/qtest.h"

#include "hw/sysbus.h"

#include "net/net.h"

#include "hw/arm/arm.h"
@@ -129,13 +128,6 @@ exynos4_boards_init_common(MachineState *machine, 
                           Exynos4BoardType board_type)

{

    Exynos4BoardState *s = g_new(Exynos4BoardState, 1);

    MachineClass *mc = MACHINE_GET_CLASS(machine);



    if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) {

        error_report("%s board supports only %d CPU cores, ignoring smp_cpus"

                     " value",

                     mc->name, EXYNOS4210_NCPUS);

    }



    exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];

    exynos4_board_binfo.board_id = exynos4_board_id[board_type];
@@ -189,6 +181,8 @@ static void nuri_class_init(ObjectClass *oc, void *data) 
    mc->desc = "Samsung NURI board (Exynos4210)";

    mc->init = nuri_init;

    mc->max_cpus = EXYNOS4210_NCPUS;

    mc->min_cpus = EXYNOS4210_NCPUS;

    mc->default_cpus = EXYNOS4210_NCPUS;

    mc->ignore_memory_transaction_failures = true;

}
@@ -205,6 +199,8 @@ static void smdkc210_class_init(ObjectClass *oc, void *data) 
    mc->desc = "Samsung SMDKC210 board (Exynos4210)";

    mc->init = smdkc210_init;

    mc->max_cpus = EXYNOS4210_NCPUS;

    mc->min_cpus = EXYNOS4210_NCPUS;

    mc->default_cpus = EXYNOS4210_NCPUS;

    mc->ignore_memory_transaction_failures = true;

}

hw/arm/highbank.c

+15 −2
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 
#include "hw/ide/ahci.h"

#include "hw/cpu/a9mpcore.h"

#include "hw/cpu/a15mpcore.h"

#include "qemu/log.h"



#define SMP_BOOT_ADDR           0x100

#define SMP_BOOT_REG            0x40
@@ -117,14 +118,26 @@ static void hb_regs_write(void *opaque, hwaddr offset, 
        }

    }



    if (offset / 4 >= NUM_REGS) {

        qemu_log_mask(LOG_GUEST_ERROR,

                  "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);

        return;

    }

    regs[offset / 4] = value;

}



static uint64_t hb_regs_read(void *opaque, hwaddr offset,

                             unsigned size)

{

    uint32_t value;

    uint32_t *regs = opaque;

    uint32_t value = regs[offset/4];



    if (offset / 4 >= NUM_REGS) {

        qemu_log_mask(LOG_GUEST_ERROR,

                  "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset);

        return 0;

    }

    value = regs[offset / 4];



    if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {

        value |= 0x30000000;