Commit 55db5eee authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging 



X86 fixes, 2015-11-17

Two X86 fixes, hopefully in time for -rc1.

# gpg: Signature made Tue 17 Nov 2015 19:06:53 GMT using RSA key ID 984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"

* remotes/ehabkost/tags/x86-pull-request:
  target-i386: Disable rdtscp on Opteron_G* CPU models
  target-i386: Fix mulx for identical target regs

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents c27e9014 33b5e8c0

include/hw/i386/pc.h

+17 −0
Original line number Diff line number Diff line
@@ -347,8 +347,25 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); 
            .driver   = "qemu32" "-" TYPE_X86_CPU,\

            .property = "popcnt",\

            .value    = "on",\

        },{\

            .driver   = "Opteron_G2" "-" TYPE_X86_CPU,\

            .property = "rdtscp",\

            .value    = "on",\

        },{\

            .driver   = "Opteron_G3" "-" TYPE_X86_CPU,\

            .property = "rdtscp",\

            .value    = "on",\

        },{\

            .driver   = "Opteron_G4" "-" TYPE_X86_CPU,\

            .property = "rdtscp",\

            .value    = "on",\

        },{\

            .driver   = "Opteron_G5" "-" TYPE_X86_CPU,\

            .property = "rdtscp",\

            .value    = "on",\

        },





#define PC_COMPAT_2_3 \

        PC_COMPAT_2_4 \

        HW_COMPAT_2_3 \

target-i386/cpu.c

+8 −4
Original line number Diff line number Diff line
@@ -1244,8 +1244,9 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_DE | CPUID_FP87,

        .features[FEAT_1_ECX] =

            CPUID_EXT_CX16 | CPUID_EXT_SSE3,

        /* Missing: CPUID_EXT2_RDTSCP */

        .features[FEAT_8000_0001_EDX] =

            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |

            CPUID_EXT2_LM | CPUID_EXT2_FXSR |

            CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |

            CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |

            CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
@@ -1273,8 +1274,9 @@ static X86CPUDefinition builtin_x86_defs[] = { 
        .features[FEAT_1_ECX] =

            CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |

            CPUID_EXT_SSE3,

        /* Missing: CPUID_EXT2_RDTSCP */

        .features[FEAT_8000_0001_EDX] =

            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |

            CPUID_EXT2_LM | CPUID_EXT2_FXSR |

            CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |

            CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |

            CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
@@ -1305,8 +1307,9 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |

            CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |

            CPUID_EXT_SSE3,

        /* Missing: CPUID_EXT2_RDTSCP */

        .features[FEAT_8000_0001_EDX] =

            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |

            CPUID_EXT2_LM |

            CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |

            CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |

            CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
@@ -1340,8 +1343,9 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |

            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |

            CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,

        /* Missing: CPUID_EXT2_RDTSCP */

        .features[FEAT_8000_0001_EDX] =

            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |

            CPUID_EXT2_LM |

            CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |

            CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |

            CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |

target-i386/translate.c

+3 −1
Original line number Diff line number Diff line
@@ -3848,8 +3848,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, 
                    break;

#ifdef TARGET_X86_64

                case MO_64:

                    tcg_gen_mulu2_i64(cpu_regs[s->vex_v], cpu_regs[reg],

                    tcg_gen_mulu2_i64(cpu_T[0], cpu_T[1],

                                      cpu_T[0], cpu_regs[R_EDX]);

                    tcg_gen_mov_i64(cpu_regs[s->vex_v], cpu_T[0]);

                    tcg_gen_mov_i64(cpu_regs[reg], cpu_T[1]);

                    break;

#endif

                }