Commit 550929dd authored by Peer Adelt's avatar Peer Adelt Committed by Bastian Koppelmann
Browse files

target-tricore: Added new MOV instruction variant 



Puts the content of data register D[a] into E[c][63:32] and the
content of data register D[b] into E[c][31:0].

[BK: fix style error]
[BK: Allocate temporaries only when needed]
Signed-off-by: default avatarPeer Adelt <peer.adelt@c-lab.de>
Message-Id: <1465314555-11501-4-git-send-email-peer.adelt@c-lab.de>
Signed-off-by: default avatarBastian Koppelmann <kbastian@mail.uni-paderborn.de>
parent ddd7fead

target/tricore/translate.c

+16 −0
Original line number Diff line number Diff line
@@ -6034,6 +6034,8 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) 
    uint32_t op2;

    int r3, r2, r1;



    TCGv temp;



    r3 = MASK_OP_RR_D(ctx->opcode);

    r2 = MASK_OP_RR_S2(ctx->opcode);

    r1 = MASK_OP_RR_S1(ctx->opcode);
@@ -6224,6 +6226,20 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) 
    case OPC2_32_RR_MOV:

        tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);

        break;

    case OPC2_32_RR_MOV_64:

        if (tricore_feature(env, TRICORE_FEATURE_16)) {

            temp = tcg_temp_new();



            CHECK_REG_PAIR(r3);

            tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);

            tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);

            tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);



            tcg_temp_free(temp);

        } else {

            generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);

        }

        break;

    case OPC2_32_RR_NE:

        tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],

                           cpu_gpr_d[r2]);

target/tricore/tricore-opcodes.h

+1 −0
Original line number Diff line number Diff line
@@ -1062,6 +1062,7 @@ enum { 
    OPC2_32_RR_MIN_H                             = 0x78,

    OPC2_32_RR_MIN_HU                            = 0x79,

    OPC2_32_RR_MOV                               = 0x1f,

    OPC2_32_RR_MOV_64                            = 0x81,

    OPC2_32_RR_NE                                = 0x11,

    OPC2_32_RR_OR_EQ                             = 0x27,

    OPC2_32_RR_OR_GE                             = 0x2b,