+24
−0
Loading
MIPS Jazz chipset doesn't seem to raise data bus exceptions on invalid accesses. However, there is no easy way to prevent them. Creating a big memory region for the whole address space doesn't prevent memory core to directly call unassigned_mem_read/write which in turn call cpu->do_unassigned_access, which (for MIPS CPU) raise an data bus exception. This fixes a MIPS Jazz regression introduced in c658b94f. Signed-off-by:Hervé Poussineau <hpoussin@reactos.org> Reviewed-by:
Paolo Bonzini <pbonzini@redhat.com> Signed-off-by:
Hervé Poussineau <hpoussin@reactos.org> Message-id: 1383603977-7003-1-git-send-email-hpoussin@reactos.org Signed-off-by:
Anthony Liguori <aliguori@amazon.com>